8VSB芯片的层次式设计方法

提出了深亚微米下系统级芯片层次式版图设计的方法，并用该方法设计了HDTV信道解码芯片8VSB的版图。实例设计结果表明，该方法在节约面积、加速时序收敛方面效果明显，大大缩短了芯片设计周期。     

大型往复式压缩机的配管设计

大型往复式压缩机功率大、占地面积大,管道振动问题也更为突出。笔者结合实践经验,对大型往复式压缩机的配管设计进行探讨,说明了平面布置与管道防振设计的密切关系,并介绍了管道防振设计的方法和步骤,以及相对简单的复杂管系气柱固有频率的转移矩阵计算方法。     

挖金湾矿近距离煤层联合布置开采可行性研究

提出挖金湾矿近距离煤层联合布置开采方案，并对开采方案的技术难点进行了分析，找出了解决方法。     

I/OIMAGESYSTEM微波中继应用

微波中继的应用非常广泛 ,目前在二维、三维施工中跨越障碍物时 ,一般都使用微波中继站来传输命令和数据。文章就微波中继及I/OIMAGESYSTEM“蛇形排列”先进功能的实际应用进行了详细的阐述 ,同时提出了使用微波中继站应注意的问题。     

马家河水电站的设计

马家河水电站通过在马家河和毛家河上游分别建底栏栅坝和低拱坝 ,经各自的引水系统将水引至两河口汇合流入前池发电。本文介绍了电站的开发方案 ,厂区、引水工程和取水枢纽的布置和设计     

32位MIPS微处理器中乘法器的设计和实现

在Booth算法的基础上,结合MIPS 4KC微处理器中的流水线结构和乘法器的工作过程,提出了一种改进的Booth乘法器的设计方法,并采用全制定方法实现,用这种方法实现的乘法器单元具有面积小、单元电路可重复性好、版图设计工作量小、功耗低等特点.     

Facility layout problems: A survey

Layout problems are found in several types of manufacturing systems. Typically, layout problems are related to the location of facilities (e.g., machines, departments) in a plant. They are known to greatly impact the system performance. Most of these problems are NP hard. Numerous research works related to facility layout have been published. A few literature reviews exist, but they are not recent or are restricted to certain specific aspects of these problems. The literature analysis given here is recent and not restricted to specific considerations about layout design.

We suggest a general framework to analyze the literature and present existing works using such criteria as: the manufacturing system features, static/dynamic considerations, continual/discrete representation, problem formulation, and resolution approach. Several research directions are pointed out and discussed in our conclusion.     

利用相对坐标轻松完成网格袋布局

网格袋布局管理器是java布局中最有用、最灵活、最复杂、最难掌握的一种布局管理器,实际上,如果我们明白了在布局时它利用了单元格相对坐标定位这一点,以及各个约束条件在布局中的作用,网格袋布局也会变得很轻松。     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.