Common Mode Voltage Reduction Using 3D-SVPWM for 3-level CI-NPC Inverter with Hybrid Energy System

This paper elucidates Common Mode Voltage (CMV) reduction in transformerless 3-phase 3-level Coupled Inductor Neutral Point (CI-NPC) Clamped Inverter with Hybrid Energy System. The three dimensional Space Vector Pulse Width Modulation (3D-SVPWM) with Nearest State Vector (NSV) is implemented to reduce the CMV by proper selection of medium, large and small vectors in 3D cubic space region. This NSV scheme in addition to CMV reduction, reduces the capacitor voltage balancing issues and minimizes switching losses. The proposed control provides full utilization of dc link voltage with reduced harmonics. This 3-level CI-NPC inverter is energized by hybrid energy source which includes photovoltaic system and wind energy system. The results obtained for the proposed scheme through simulation and experimental setup is compared with the conventional 2D-SVPWM and 3D-SVPWM scheme. From the compared results it is evident that the proposed scheme reduces CMV to a larger extent than 2D and 3D-SVPWM control. The simulation and experimental results are verified using matlab-simulink and FPGA-Spartan-6 controller respectively.     

基于BEPCⅡ数字束流位置测量系统电子学系统的设计与实现

BEPCⅡ加速器的束流位置测量系统（BPM）模拟电子学经过十余年的运行逐渐老化，故障率上升，亟需进行升级改造。本文根据该需求，自行设计了基于BEPCⅡ系统参数的数字BPM电子学系统，内容包括模拟信号处理电子学、数字信号处理电子学、BPM固件算法逻辑、数据获取软件以及系统测试等多个部分。设计的数字BPM电子学系统经实验板级性能测试、实验室系统测试以及在线束流测试，结果表明该系统能满足BEPCⅡ装置对束流位置测量的需求。     

Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard

Two low-memory and high-performance architectures for the CCSDS 122.0-B-1 standard are proposed. They use novel memory organizations to reduce the total memory requirements in order to be implemented in a single FPGA device. The architectures were implemented in radiation-hardened and commercial FPGA devices. Based on the experimental results for the case of Virtex5QV radiation-hardened device, the throughput is 135 MSamples/sec for image with 12 bits/pixel and horizontal resolution up 8192 pixels. Also, the proposed architectures outperform the existing one in terms of the memory requirements and area.     

Model-Based Design Space Exploration for FPGA-based Image Processing Applications Employing Parameterizable Approximations

The increasing demand for low power consumption and high computational performance is outpacing available technological improvements in embedded systems. Approximate computing is a novel design paradigm trying to bridge this gap by leveraging the inherent error resilience of certain applications and trading in quality to achieve reductions in resource usage. Numerous approximation methods have emerged in this research field. While these methods are commonly demonstrated in isolation, their combination can increase the achieved benefits in complex systems. However, the propagation of errors throughout the system necessitates a global optimization of parameters, leading to an exponentially growing design space. Additionally, the parameterization of approximated components must consider potential cross-dependencies between them. This work proposes a systematic approach to integrate and optimally configure parameterizable approximate components in FPGA-based applications, focusing on low-level but high-bandwidth image processing pipelines. The design space is explored by a multi-objective genetic algorithm which takes parameter dependencies between different components into account. During the exploration, appropriate models are used to estimate the quality-resource trade-off for probed solutions without the need for time-consuming synthesis. We demonstrate and evaluate the effectiveness of our approach on two image processing applications that employ multiple approximations. The experimental results show that the proposed methods are able to produce a wide range of Pareto-optimal solutions, offering various choices regarding the desired quality-resource trade-off.     

FPGA互连测试中的反馈桥接故障覆盖问题

现场可编程门阵列(FPGA)内部资源众多,其中互连资源出现故障的概率远远高于片内其他资源,而在以往许多互连测试研究中,所生成的测试配置存在无法覆盖反馈桥接故障的难题,所以较难有测试配置实现故障列表的100%覆盖。因此通过约束桥接故障只发生在单个查找表(LUT)内的信号线上,并结合单项函数,对反馈桥接故障模型进行优化改进,从根本上解决难题；然后对优化后的反馈桥接故障设置相应的约束条件,再使用布尔可满足性理论(SAT)生成满足约束条件的测试配置。采用优化后的故障模型对ISCAS"89基准电路进行了测试配置生成实验,结果表明生成的测试向量解决了反馈桥接故障的覆盖难题,并且在实现故障列表的100%覆盖下,优化后的故障模型所需要的测试配置数最少。     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

FPGA设计的层次化实验项目的构建

数字电子技术是电子信息类的专业技术基础课程,一方面近些年可编程技术的发展及应用,改变了数字系统的设计理念、设计方法,传统的基于原理图和中小规模集成电路的设计方法已被FPGA所取代,HDL已经成为数字设计技术主流；另一方面在当前“新工科”理念下,要培养具有工程实践能力的人才,但传统工科教育的课程架构却难以满足这一要求。课程内容必须跟上时代发展,要服务社会,那么课程与教学内容的改革是无法回避的,本文以传统数字电子技术为基础,结合实际案例,从点、线、面、体四个层次设计实验项目,让学生快速入手并掌握FPGA的设计。     

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.