气体开关串级环形间隙放电相互影响机制研究

针对中空和非中空触发电极结构的两间隙开关，进行了触发击穿特性实验，对比两个间隙的击穿抖动和通道数，分析了串级两间隙的相互影响机制。实验结果表明：两只开关触发间隙击穿抖动和通道数变化规律基本一致；非中空开关自击穿间隙击穿抖动随工作系数的增大而减小，最小约3 ns，中空开关自击穿间隙击穿抖动始终约1 ns；非中空开关自击穿间隙难形成多通道放电，中空开关自击穿间隙通道数明显多于其他间隙。触发间隙首先放电产生紫外光，通过触发电极中空通孔预先照射自击穿间隙产生初始电子，是自击穿间隙击穿抖动减小、通道数增加的主要作用机制。     

接触器触头系统振动机理分析及算法优化

为了解决合闸过程中动、静触头接触引起的振动弹跳问题.本文建立了接触系统的二自由度运动微分方程,并利用遗传算法对交流接触器吸合过程进行优化,同时通过高速摄影实验对接触弹跳的全过程进行了观察和分析.结果表明:理论与实验结果高度一致,铁心在触头分离前发生碰撞,进一步加剧触头弹跳;铁芯弹跳再次碰撞时,触头的弹跳不受影响;在接触器运行过程中,动铁芯的运动会引起系统轻微振动;采用遗传算法优化的接触器触头弹跳时间和最大振幅均减小.研究结果为进一步控制和减小接触弹跳提供了理论依据.     

Turncoat Polypeptides: We Adapt to Our Environment

A common interpretation of Anfinsen's hypothesis states that one amino acid sequence should fold into a single, native, ordered state, or a highly similar set thereof, coinciding with the global minimum in the folding-energy landscape, which, in turn, is responsible for the function of the protein. However, this classical view is challenged by many proteins and peptide sequences, which can adopt exchangeable, significantly dissimilar conformations that even fulfill different biological roles. The similarities and differences of concepts related to these proteins, mainly chameleon sequences, metamorphic proteins, and switch peptides, which are all denoted herein “turncoat” polypeptides, are reviewed. As well as adding a twist to the conventional view of protein folding, the lack of structural definition adds clear versatility to the activity of proteins and can be used as a tool for protein design and further application in biotechnology and biomedicine.     

GIS气体高压开关在阳煤五矿变电站的应用

针对阳煤五矿广场变电站的高压开关老化问题,为了保证安全性,采用了GIS气体的高压绝缘开关进行了改造。在改造后,变电站的安全性得到了显著提高,设备运行可以节省成本200多万元。     

雷达发射机浮动板调制器与故障检测电路的设计

提出了一种改进的浮动板调制器和对正负偏电压的故障检测电路,利用MOSFET寄生电容特性,通过固定脉宽窄脉冲控制调制脉宽,通过增加负偏MOSFET提高输出负偏电压。对故障检测电路进行仿真实验,通过模拟故障,验证故障检测报警信号发生时间均在微秒级别。完成样机的搭建,利用多重方式解决高压绝缘问题,并对其加电进行试验验证,分析实验波形,证明此电路满足设计要求并且具有可行性。     

Homogeneous and Universal Detection of Various Targets with a Dual-Step Transduced Toehold Switch Sensor

Toehold switch sensors represent a class of new advances that allow specific targets to trigger in situ expression of a protein reporter. Although they offer unique advantages of a label-free nature and high portability, they generally require repeated sequence design, high expenditure, and laborious optimization of toehold switch sequences according to different targets. To simplify the sensing process further and to improve its practicability, we innovatively introduce a dual-step pre-transduction upon traditional toehold switch sensor. Through two successive toehold-mediated strand-displacement reactions that are initiated, respectively, by a linear and an associative trigger, different DNAs, RNAs, or ligands of functional nucleic acids can be generally transduced into the input of one high-performance toehold switch sensor. This advance greatly increases the target range. Furthermore, the whole process is signal-on, homogeneous, and free of any requirements for complicated operations such as probe labeling, separation, and reconstruction of the toehold switch, being promising and practical even in portable or point-of-care assays.     

A voltage support control strategy based on three-port flexible multi-state switch in distribution networks

Voltage sags in power system may lead to serious problems such as the off-grid of distributed generation and electrical equipment failures. As a novel type of power electronic equipment, a flexible multi-state switch (FMSS) is capable to support the voltage during the grid faults. In this paper, a voltage control strategy to support the voltage in a distribution network is proposed by introducing three-port FMSS. The positive–negative-sequence compensation (PNSC) scheme is adopted to control the active and reactive current. This control scheme eliminates active power oscillations at the port of voltage sags and reduces coupling oscillations of other ports. Based on the characteristics of the voltage support under PNSC scheme, two voltage support strategies are proposed. A proportional-integral controller is introduced to provide the reactive power references, which eliminates the errors when estimating the grid voltage and impedance. A current limiting scheme is adopted to keep the port current in a safe range by adjusting the active and reactive power references. The voltage support strategies in two different voltage sags are simulated, and results show the feasibility and effectiveness of the proposed control strategies.     

基于有限元分析的强迫对流条件下开关柜温升特性研究

12kV大电流开关柜广泛用于配电网中,一般采取强迫对流的方式进行散热。为研究开关柜在强迫对流条件下的散热过程,基于有限元仿真技术,分别分析了强迫鼓风和抽风两种条件下开关柜的散热能力。通过对开关柜进行三维建模、热源计算和边界条件设立,仿真分析了开关柜在强迫鼓风和抽风条件下的温升分布及气流场分布情况,并与试验结果进行对比。结果表明,开关柜在两种强迫对流条件下散热效果均较好,温升符合国标温升要求,但不同的散热方式对开关柜温升和气流场分布影响较大。     

矿用组合开关保护系统研究

简要介绍了本安先导电路的判定及继电器隔离方式的本安先导电路原理,运用3种方法分析了矿井低压电网漏电故障,最后在此基础上,从组合开关对电压保护、短路保护和过载保护三个方面,详细探讨了基于组合开关的矿井低压电网保护,相信可以通过多方面的综合分析研究出更可靠、保护更加全面和智能的组合开关,从而为中国井下煤矿的安全机械化开采提供更有保障的服务。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.