Characterisation of Saccharomyces cerevisiae ARO8 and ARO9 genes encoding aromatic aminotransferases I and II reveals a new aminotransferase subfamily

It is known that lpr mice develop systemic lymphadenopathy and lupus erythematosus-like autoimmune disease that are associated with the accumulation of CD4- CD8- (double-negative; DN) CD3+ B220+ abnormal T cells as well as normal mature CD4+ or CD8+ single-positive (SP) CD3+ T cells. In order to clarify the role of B cells in the lymphoproliferation and autoimmunity of lpr mice, we created B-cell-deficient C57BL/6 (B6) lpr mice (B6lpr/lpr microMT/microMT) by crossing B6lpr/lpr mice with B6 microMT/microMT mice in which the B-cell development was arrested at pre-B stage owing to a targeted disruption of the immunoglobulin mu heavy-chain gene locus. In the B-cell-deficient B6-lpr mice, both lymphadenopathy and splenomegaly were markedly suppressed. Although the accumulation of both CD3+ B220- SP normal T cells and CD3+ B220+ DN abnormal T cells was inhibited in the B-cell-deficient lpr mice, the decrease in numbers of CD3+ B220- SP normal T cells occurred more strikingly than that of the CD3+ B220+ DN abnormal T cells. Glomerulonephritis did not develop in the B-cell-deficient lpr mice over 40 weeks. The present results indicate that the B cells thus play a crucial role in the extensive proliferation of normal CD3+ B220- mature SP T cells rather than the accumulation of abnormal DN T cells.     

Marketing Activities to Support ‘Moderately Novel’ Product Innovation: Insights from the Chemical Industry

Scholars often follow a contingency approach to study which marketing activities are suitable for a particular type of product innovation project, thereby making a distinction between incremental and radical innovation only. ‘Moderately novel’ projects, which have intermediate levels of newness, have therefore not been given due attention. This paper focuses on market intelligence generation and the creation of cross‐functional linkages as marketing activities that are important in the context of moderately novel product innovation. In addition, the organizational position of the marketers involved in these activities is dealt with. Based on the analysis of four successful projects in the chemical industry, we argue, firstly, that moderately novel innovation projects have their own particular sets of marketing practices and, secondly, that differences exist between projects aiming at a new market segment and projects in which novelty is not related to market segment but to other market dimensions. These differences are especially salient in early project phases. These findings are pertinent to research on the role of marketers in product innovation, and to the study of organizational ambidexterity.     

Software-programmable digital pre-distortion on new generation FPGAs

In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among the hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used Vivado high-level synthesis (HLS) tool as the design tool for the programmable logic. Furthermore, we have compared two different techniques for the integration of hardware and software components, where we have chosen the one with better area/latency trade-off. We present a comprehensive study reporting the DPD parameter update times when exploring the partitioning of the functionality among hardware and software. For low-complexity algorithms, we show that a software-only solution is applicable after carrying out the processor-specific software optimizations. For higher-complexity algorithms, we use Vivado HLS to accelerate the time-consuming blocks in the programmable logic, leading to a speed-up factor of up to 7× in the overall algorithm execution time. We present the performance results for two target devices. We also show that our accelerators use only a small portion of the programmable logic fabric on these devices and that a significant reduction of the system’s energy consumption can be obtained by leveraging the FPGA fabric.     

Development of a Broadband NbTiN Traveling Wave Parametric Amplifier for MKID Readout

The sensitivity of microwave kinetic inductance detectors (MKIDs) using dissipation readout is limited by the noise temperature of the cryogenic amplifier, usually a HEMT with \(T_n \sim \) 5 K. A lower noise amplifier is required to improve NEP and reach the photon noise limit at millimeter wavelengths. Eom et al. have proposed a kinetic inductance traveling wave (KIT) parametric amplifier (also called the dispersion-engineered travelling wave kinetic inductance parametric amplifier) that utilizes the nonlinearity with very low dissipation of NbTiN. This amplifier has the promise to achieve quantum limited noise, broad bandwidth, and high dynamic range, all of which are required for ideal MKID dissipation readout. We have designed a KIT amplifier which consists of a 2.2 m long coplanar waveguide transmission line fabricated in a double spiral format, with periodic loadings and impedance transformers at the input/output ports on a 2 by 2 cm Si chip. The design was fabricated with 20 nm NbTiN films. The device has shown over 10 dB of gain from 4 to 11 GHz. We have found the maximum gain is limited by abrupt breakdown at defects in the transmission line in the devices. By cascading two devices, more than 20 dB of gain was achieved from 4.5 to 12.5 GHz, with a peak of \(\sim \) 27 dB.     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

Crosspolarisation properties of reflector antennas with random surface errors

The crosspolarisation properties of symmetric front-fed paraboloids with random surface errors are investigated. Average crosspolar far-field patterns and crosspolarisation discriminations are computed for different RMS surface errors. The influence of the correlation interval and phase-error model used is indicated.     

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.