排序方式: 共有49条查询结果,搜索用时 15 毫秒
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HUANG Songren CHEN Zhenhai ZHANG Hong LI Xue QIAN Hongwen YU Zongguang 《西安电子科技大学学报(自然科学版)》2016,43(6):170-175
A 1.5bit sub-stage circuit based on bucket-brigade devices (BBD) for high speed charge domain pipelined ADCs is presented to solve the problem that the performances of high-speed, high-resolution ADCs rely on the opamps with large gain-bandwidth production, which results in large power consumption. Charge transfer and residue charge calculation are realized with a boosted charge transfer (BCT) circuit in the proposed 1.5bit sub-stage, and therefore, the high-performance opamps in traditional pipelined ADCs are eliminated and the power consumption can be reduced remarkably. Based on the proposed 1.5bit sub-stage circuit, a 10bit 250MS/s charge domain pipelined ADC is designed in 0.18μm CMOS technology. Measurement results under a sampling frequency of 250MHz and an input sinusoidal frequency of 9.9MHz show that the ADC achieves a spurious free dynamic range (SFDR) of 64.4dB and a signal-to-noise-and-distortion ration(SNDR) of 56.9dB, with power consumption of only 45mW. 相似文献
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一种采用PVT不敏感电荷传输电路的27mW 10位125MSPS 电荷域流水线模数转换器 总被引:2,自引:2,他引:0
A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm~2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively. 相似文献
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可靠性筛选是提高电子产品良率的重要技术手段。针对绝缘体上硅(SOI)技术日益广泛的应用,通过大量实验研究了SOI电路的常用筛选试验,并对失效样品进行了相应的失效机理研究。首先讨论了SOI电路失效模式和筛选方法之间的关系;其次,针对三款SOI电路分别开展了老炼应力、高温贮存及恒定加速度试验来进行可靠性筛选;最后,利用光发射显微镜、扫描电子显微镜、聚焦离子束和激励源诱导故障测试等失效分析手段,对失效样品进行了失效模式及机理分析,揭示了失效根源,为改进工艺、提高SOI电路可靠性提供了依据。 相似文献
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随着ADC测试技术的不断发展,码密度直方图技术以及采用正弦波输入的离散傅里叶变换(DFT)频域分析技术已经被广泛应用到ADC的仿真和测试分析中。相对于采用DFT进行频域分析获取ADC的动态性能的复杂性来说,采用码密度直方图的方法能简单地得到微分非线性(DNL)和积分非线性(INL)这两个静态性能指标。文章通过对一个10位ADC的行为级模型的仿真分析,阐述了总谐波失真(THD)与INL之间的内在联系,从而提出了通过对INL的测试来评估ADC的THD性能的方法,对今后ADC电路的测试和评估具有指导意义。 相似文献
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硅控整流器SCR作为晶闸管常用于功率器件,具有再生性和从高阻态到低阻态切换的能力.因此合理设计的SCR能成为非常高效的ESD保护电路.文章介绍了SCR的基本机制,SCR、MLSCR、LVTSCR和SCR组合保护电路的结构,并介绍了具有更好ESD性能的设计和版图. 相似文献
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CHEN Zhenhai WEI Jinghe SU Xiaobo ZOU Jiaxuan ZHANG Hong YU Zongguang 《西安电子科技大学学报(自然科学版)》2017,44(6):109
A feed-forward common-mode(CM) charge compensation circuit and a foreground calibration technique for the high speed charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented to solve the problem that the precision of CD pipelined ADCs is restricted by the variation of the input CM charge and the offset error. The proposed compensation circuit and the calibration technique can compensate the CM charge and errors caused by the variation of the input CM charge and offset respectively. Based on the feed-forward CM charge compensation circuit and the offset error foreground calibration technique, a 12bit 500MS/s time-interleaved CD pipelined ADC is designed and realized in a 1P6M 018μm CMOS process. The ADC achieves the spurious free dynamic range (SFDR) of 775dB and the signal-to-noise-and-distortion ratio (SNDR) of 627dBFS for a 199MHz input at a full sampling rate. The variation of signal-to-noise ratio is less than 3dB for the input CM voltage in the 0 to 12V range. The power consumption of the prototype ADC is only 220mW at 18V supply and occupies the active die area of 624mm2. 相似文献
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本文提供了一种低功耗电荷域10位250Msps电荷域流水线模数转换器(ADC)。通过采用基于BBD的电荷域流水线技术实现,使得ADC具有超低功耗;通过采用一种Replica控制PVT波动不敏感BCT电路,在不降低电荷传输速度的条件下抑制了PVT波动敏感性。采用0.18um CMOS工艺,在没有采用共模控制和误差校准技术的条件下,所实现的10位电荷域ADC在250MHz全速采样时对于9.9MHz正弦输入信号转换得到的无杂散动态范围(SFDR)为64.74dB,信噪失真比(SNDR)为56.9dB,有效位数(ENOB)达9.1比特,最大微分线性度(DNL)为 0.5/-0.5 LSB,最大积分线性度(INL)为 0.8/-0.85 LSB,并且在1.8V电源条件下整个电路功耗仅为45mW,整个ADC有源芯片面积为1.2×1.3 mm2。 相似文献
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功率VDMOS器件用硅外延材料研制 总被引:1,自引:1,他引:0
文章阐述了硅功率VDMOS器件的基本原理和器件结构,也展现了作为电力电子器件其广阔的应用领域,提出了功率VDMOS器件对硅外延材料的要求和发展方向。依据功率器件对外延片的要求,通过优化外延工艺程序和优化外延工艺参数,消除或减弱了自掺杂对电阻率均匀性的影响,消除了过渡区对厚度均匀性的影响,也较好地控制了外延层中的结构缺陷... 相似文献
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