Fabrication of a poly-Si thin-film transistor with storage capacitor

The fabrication process of a low-temperature poly-Si thin-film transistor (TFT) with a storage capacitor was studied. The atmospheric-pressure chemical-vapour deposited SiO₂ protected the buried indium tin oxide (ITO) from reduction by a pure H₂ plasma treatment that was essential for the effective improvement of the poly-Si TFT characteristics. Thus, a storage capacitor with an ITO (picture electrode)-SiO₂-ITO (buried common electrode) structure was successfully fabricated. The poly-Si TFT with a channel width/length W/L ratio of 5 drove a 3 pF storage capacitor in 2 μs, and it showed superior driverability for LCD use. The TFT also had good hold characteristics under illumination for the realization of grey-scale representation.     

Stabilization of inter-area and/or oscillatory modes in large-scale power system by voltage impedance power system (VIPS) apparatus based on decentralized control scheme

New technologies such as power electronics have made it possible to change continuously the impedance of a power system not only to control power flow but also to enhance stability. A power system incorporating a variable impedance apparatus such as a variable series capacitor (VSrC) and high-speed phase shifter (HSPS) is called VIPS (Variable Impedance Power System) by the authors. This paper proposes a novel control method of VIPS apparatus such as VSrC and HSPS installed at an interconnecting point for stabilizing inter-area unstable and/or oscillatory modes. The proposed design method of the control system is a kind of hierarchical decentralized control method of a large-scale power system based on a Lyapunov function. Under the proposed control scheme, each subsystem can be stabilized independently by local controllers such as AVR, speed governor and PSS, and then the whole interconnected system can be stabilized by VIPS apparatus taking into account interactions between subsystems. The effectiveness and robustness of the VIPS apparatus control are shown by numerical examples with model systems including a large-scale power system.     

用于高压电容器的SrTiO3基陶瓷

报道ＳｒＴｉＯ３基陶瓷的制备方法和介电性质，给出了用此种陶瓷制成的高压电容器的试验结果，并对它位进行了讨论。     

一种基于混沌的随机数发生器设计及其IC实现

在密码学、仿真学以及集成电路测试等许多领域 ,随机数起着重要的作用。在密码学中 ,通常要求所使用的随机数具有不可预测性。基于混沌现象 ,使用开关电容技术 ,用集成电路实现了一种硬件随机数发生器。测试结果表明 ,其产生的序列具有不可预测性 ,可以满足密码学的应用要求。     

开关电流技术：一种新的模拟抽样数据处理方法

开关电流（ＳＩ）技术是一种新的模拟抽样数据处理技术，介绍了开关电流电路的基本单元结构，讨论了目前开关电流技术中存在的问题及其解决方法。对开关电流技术与开关电容技术的一些基本特征进行了比较，ＳＩ技术不仅结构简单，而且与标准ＣＭＯＳ工艺兼容，可望替代开关电容电路。     

片式阻容元件的现状和发展方向

在国外的片式元器件（ＳＭＤ）中，片式阻容元件发展最快，主要表现为片式化率迅速上升，尺寸越来越小，性能越来越好，包装形式多样化和生产管理不断改进。本文综述了国外阻容元件在这些方面的进展，指出了我国的差距，提出了我国如何发展的措施。     

本征吸除硅片特性研究

本文描述硅本征吸杂片的特性参数,如吸除区宽度、洁净度,氧沉淀密度、MOS电容寿命,介绍了表面态密度及残余间隙氧浓度的检测方法和工艺对参数的影响及参数之间的内在联系,文章还实验论证了不同参数水平对器件成品率的影响,建立了以MOS电容寿命为主导的参数控制方法,利用本文提供的控制参数,可使CCD-512器件成品率达60％,以上优品率≥85％。     

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.     

基于小波熵的电容器扰动识别和定位

对投电容器扰动识别和定位的方法进行了改进。针对其他此类方法的不足，比如在电压幅值低时投电容器扰动的识别、定位“可信度不高”等，文中通过提取小波变换的特定层的系数，对需要识别的电容器扰动的分解信号相对增强，而其他扰动的分解信号相对减弱，然后再提取熵特征值，结果表明它可以作为识别低电压时投电容器扰动的依据。在对电容器扰动进行定位时，参考了功率和能量定位法，并对其进行了改进。仿真分析证明，在电压幅值较低时，可以准确和可靠地对电容器扰动进行识别和定位。     

脉冲激光沉积SrBi2Ta2O9铁电薄膜电容特性研究

用ＰＬＤ方法成功地制备了ＳＢＴ铁电薄膜，并制作成Ｐｔ／ＳＢＴ／Ｐｔ薄膜电容器。ＳＢＴ薄膜的晶面取向以（００８）和（１１５）为主。在５Ｖ电压下，极化反转，并且得到较饱和的电滞回线，剩余极化强度和矫顽电场分别为８４μＣ／ｃｍ２和５７ｋｖ／ｃｍ。ＩＶ特性测试显示两个对称的双稳峰，并得到零电压下，面积为３１４×１０４μｍ２，厚度为０３５μｍ的电容器，电容约为５６０ｐＦ，介电常数约为６００。疲劳测试表明Ｐｔ／ＳＢＴ／Ｐｔ具有优良的抗疲劳特性。