Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress(MGS) in 20 nm high-k/metal-gate-last(HKVMG-last) nMOS devices.The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values(0 to—6 GPa) was implemented in the device simulation along with other traditional process-induced-strain(PIS) technologies like e-SiC and nitride capping layer.The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down.In addition,the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated.Also with a new method of fully stressed replacement metal gate(FSRMG) and using plane-shape-HfO to substitute U-shape-HfO,the effect of MGS was improved.For greater film stress in the metal gate,the process conditions for physical vapor deposition(PVD) TiN-x- were optimized.The maximum compressive stress of—6.5 GPa TiN_x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.     

20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

对于如今的CMOS集成工艺,应变金属栅是关键的工艺引入应变技术（PIS,process-induced-strain）之一。在本文中,为了在20nm高K金属栅后栅工艺的nMOS器件中得到较高栅应力,我们对金属栅结构和薄膜工艺的优化进行了大量的研究。通过TCAD工具对工艺和器件的仿真,我们研究了先进应变金属栅技术对器件性能的影响。带有不同栅应力（0GPa~-6GPa）的金属栅电极被应用在器件的仿真中,与此同时,其他PIS技术,如e-SiC 和氮化物应力层也被应用于器件中。随着器件尺寸的减小,应变金属栅对器件中沟道载流子输运有巨大的提高作用。此外,一种新型的角栅电极结构被提出,角度与沟道应力的关系被研究。同时,一种新的全应变金属填充栅以及用平板型氧化铪层代替U型氧化铪层,都能够提高应变金属栅的效果。为了在金属栅中得到更大应力的薄膜,我们优化了物理汽相淀积氮化钛的工艺条件。在氮气流量大约6sccm,较高溅射功率和较薄膜厚的情况下我们得到了最大的压应力-6.5GPa。