排序方式: 共有47条查询结果,搜索用时 15 毫秒
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An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit. 相似文献
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A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt... 相似文献
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A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads. 相似文献
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A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads. 相似文献
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本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。 相似文献
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This paper presents a 50 Hz 15-bit analog-to-digital converter(ADC) for pixel-level implementation in CMOS image sensors.The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets.The core circuit for charge/pulse conversion is specially optimized for low power,low noise and small area.An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification.The measurement result shows a standard deviation of 1.8 LSB for full-scale output.The ADC has an area of 4545 m2 and consumes less than 2 W in a standard 1P-6M 0.18 m CMOS process. 相似文献
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14位20 MS/s CMOS流水线A/D转换器 总被引:1,自引:1,他引:0
介绍了一种14位20 MS/s CMOS流水线结构A/D转换器的设计.采用以内建晶体管失配设置阈值电压的差分动态比较器,省去了1.5位流水线结构所需的±0.25 VR两个参考电平;采用折叠增益自举运算放大器,获得了98 dB的增益和900 MHz的单位增益带宽,基本消除了运放有限增益误差的影响;采用冗余编码和数字校正技术,降低了对比较器失调的敏感性,避免了余差电压超限引起的误差.电路采用0.18 μm CMOS工艺,3.3 V电源电压.仿真中,对频率1 MHz、峰值1 V的正弦输入信号的转换结果为:SNDR 85.6 dB,ENOB 13.92位,SFDR 96.3 dB. 相似文献
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采用0.8μm CMOS工艺,实现了一种用于过采样∑-△ A/D转换器的数字抽取滤波器。该滤波器采用多级结构,梳状滤波器作为首级,用最佳一致逼近算法设计的FIR滤波器作为末级,并通过位串行算法硬件实现。芯片测试表明,该滤波器对128倍过采样率、2阶∑-△调制器的输出码流进行处理得到的信噪比为75dB。 相似文献