连续时间Sigma Delta ADC设计和非理想因素分析

文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素（时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等）,基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。     

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate （BG-FP） structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance(C_gd) under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_gd than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_max are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.     

硅基PZT压电薄膜微传感器的结构设计和实验研究

对硅基锆钛酸铅(PZT)压电薄膜微传感器进行了结构和版图设计.根据MEMS加工工艺和标准硅基IC工艺的特点,获得了硅基PZT压电薄膜微悬臂梁结构系统工艺流程中的关键工艺技术和典型工艺条件.对PZT压电薄膜的制备和微细图形化进行了较为详细的实验研究,最后成功地制备出硅基PZT压电薄膜微传感器样品.这对集成化芯片系统的进一步发展打下了良好的实验基础.     

逐次逼近ADC无源器件的匹配性与高层次模型

对逐次逼近A/D转换器的无源器件匹配性进行了研究.基于理论分析,明确了电荷再分配结构、电压等比例缩放结构以及混合结构等几种典型逐次逼近A/D转换器对无源器件网络匹配性的具体要求,并利用Matlab工具,通过建立逐次逼近A/D转换器无源器件匹配性高层次模型对理论分析结果进行了验证.在此基础上提出了一种基于单位电容缩放的新型电荷再分配结构,在不提高无源器件匹配性要求的前提下,利用单位电容取代原有缩放电容并增加一定的时序控制,有效地解决了传统电容缩放结构中缩放电容工艺实现困难以及对寄生电容敏感的问题,适合片上系统的嵌入式应用.     

一种用于14位1.28MS/sΣΔADC的数字抽取滤波器设计

设计了一种数字抽取滤波器,此滤波器由多级级联结构组成,对sigma-delta调制器的输出信号进行滤波和64倍的降采样,具有较小的电路面积和较低的功耗.采用TSMC 0.18μm CMOS工艺实现,工作电压1.8V,流片测试结果表明:sigma-delta调制器输出信号经过数字抽取滤波器后,信噪失真比(SNDR)达到了93.9 dB,满足设计要求.所提出的数字抽取滤波器-6dB带宽为640kHz,抽取后的采样频率为1.28MHz,功耗为33mW,所占面积约为0.4mm×1.7mm.     

准确的FPGA互连长度和通道宽度估计

提出了一种新的FPGA互连预测算法,包括互连长度估计算法和通道宽度估计算法.实验结果表明,与现有算法相比,该估计算法能获得更准确的估计结果.     

一种稳定的RLC互连π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型,并讨论了它在互连树延时和逻辑门延时估计中的应用.结果表明,该模型与已有方法相比精度有一定程度的提高.     

改善FPGA互连阻性短路的测试能力

通过HSPICE模拟和理论分析研究了FPGA互连中的阻性短路缺陷行为.结果表明,阻性短路产生了时序故障,小电阻缺陷甚至产生了布尔故障.对于大电阻缺陷,当被测通路进行v-to-v转换,且引起短路故障的另一条通路保持v值时,最好检测方式发生.另外,使用静态分析可以很容易检测到小电阻缺陷.在最好检测方式下,评估了电源电压和温度对测试结果的影响.结果表明低电压有助于改善测试,短路材料有正温度系数时,低温测试较好,反之高温测试较好.     

基于Verilog-A行为描述模型的VCO设计

分析了模拟硬件描述语言Verilog-A的特点,介绍了基于Verilog-A语言的行为级模拟电路设计过程.以锁相环(PLL)的子模块压控振荡器(VCO)的设计为例,建立了基于Verilog-A的行为模型进行系统设计的新方法.根据VCO的数学模型,建立了中心频率为120MHz的VCO行为模型,并利用Cadence Spectre仿真器对该模型进行了验证及PLL系统仿真.     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.