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使用时间化自动机形式化带有时间扩展的UML状态图 总被引:9,自引:0,他引:9
严格建模是嵌入式实时系统设计的核心技术,通过UMI。方法与形式化方法结合可以给严格建模提供很好的工具支持。时间化自动机(Timed Automata)是一种用于描述、验证实时系统的理论模型。文中提出了一种通过时间化自动机来形式化带有时间扩展的UML状态图的方法,这种方法为UMI。与形式化方法的结合构造了桥梁作用。带有时间扩展的UML状态图用于嵌入式系统动态模型的建模,从时间化自动机模型得到形式化规范将更容易。UML状态图的形式化分为两部分完成;层次状态图的平面化以及时间化自动机的构造。 相似文献
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UML statechart based rigorous modeling of real-time system 总被引:1,自引:0,他引:1
Rigorous modeling could ensure correctness and could verify a reduced cost in embedded real-time system development for models. Software methods are needed for rigorous modeling of embedded real-time systems. PVS is a formal method with precise syntax and semantics defined. System modeled by PVS specification could be verified by tools. Combining the widely used UML with PVS, this paper provides a novel modeling and verification approach for embedded real-time systems. In this approach, we provide 1 ) a time-extended UML statechart for modeling dynamic behavior of an embedded real-time system ; 2) an approach to capture timed automata based semantics from a timed statechart; and 3 ) an algorithm to generate a finite state model expressed in PVS specification for model checking. The benefits of our approach include flexibility and user friendliness in modeling, extendability in formalization and verification content, and better performance. Time constraints are modeled and verified and is a highlight of this paper. 相似文献
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