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A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode. 相似文献
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介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90... 相似文献
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本文描述了一个高线性,高输出功率的直接变频发射机。该发射机针对宽频码分多工存取标准设计,在0.13微米CMOS工艺下实现。本系统最大输出功率为6.8dBm,消耗的电流为38mA。在最大输出功率下,邻道功率泄漏(ACLR)和载波泄漏分别为-44dBc@5MHz和-37dBc,相应的误差矢量振幅(EVM)为3.6%。整个系统可以以6dB为步长实现66dB的增益控制范围,通过电阻阵列的微调功能,增益控制精度可以达到0.1dB以内。系统的镜像抑制比可以在整个输出范围内保持在-47dBc以下。 相似文献
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低功耗输出脉冲幅度和频谱可调的超宽带发送机设计 总被引:1,自引:1,他引:0
A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm^2. 相似文献
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A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2. 相似文献
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A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2. 相似文献
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This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ... 相似文献
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