Evaluation of the pole expressions of nano-scale multistage amplifiers based on equivalent output impedance

Several frequency compensation schemes have been proposed to stabilize multistage amplifiers with negative feedback. The performance of these amplifiers can be analyzed by inspecting their input-output transfer function as representation of their frequency response. With many circuit elements affecting the output response, it is relatively difficult to obtain the real transfer function of multistage amplifiers based on only the original small-signal expressions. Instead, certain techniques such as Miller’s theorem are used to approximate important parameters such as DC gain and dominant pole. These methods are not generally helpful for approximating the nondominant poles which have a critical role on the loop stability of nano-scale amplifiers. With this issue in mind, this work proposes a systematic methodology to achieve the pole expressions of multistage amplifiers with frequency compensation. The key in the proposed technique is to model the equivalent impedance of the compensation loop at the output. The effectiveness of the proposed approach has been verified through comparison between the transfer functions obtained from theory and those transfer functions found in the literature.     

一种动态开关电容运算放大器共模负反馈电路

本文主要介绍了一种应用于Cascode结构运放中的开关电容共模负反馈电路，它具有稳定性好、对运放频率特性影响小、不消耗额外功率等优点。对电路运用Hspice进行了模拟，并给出了模拟结果。     

一种高精度带隙基准源和过温保护电路

设计了一种适用于P阱CMOS工艺的高精度带隙基准源及过温保护电路。基准源信号输出由两路电流相加实现：一路是正比于双极晶体管的发射极一基极电压的电流(IVBE)，另一路是基准源内产生的正比于绝对温度的电流(IPTAT)；同时，利用这两路电流的不同温度特性，通过直接电流比较的方法，简单地实现了高精度的过温保护电路。     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

一种高性能共模反馈CMOS运算放大器

介绍了一种具有高增益,高电源抑制比(CMRR)和大带宽的两级共源共栅运算放大器。此电路在两级共源共栅运算放大器的基础上增加共模反馈电路,以提高共模抑制比和增加电路的稳定性。电路采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真。结果显示,该放大器增益可达到101 dB,负载电容为10 pF时,单位增益带宽大约为163 MHz,共模抑制比可达101dB,电路功耗仅为0.5 mW。     

一种新颖的具有带隙结构运算放大器设计

本文提出了带隙结构的运算放大器，把带隙基准和运算放大器有机的结合到一起，有效的节省了芯片面积，并有很好的精度和动态响应特性。本文阐述了该结构的工作原理，对整体结构进行分析，重点阐述了带隙结构的特点。采用0.8μm BiCMOS工艺，通过HSPICE进行仿真验证，得到其开环增益为63.4dB，电源抑制比为106.4dB。     

低噪声无偏置电压-电流变换器

为解决电压-电流变换器电路的直流精度、噪声性能和交流性能间的矛盾,提出了一种直流部分与交流部分相对独立的电路结构.以两个对称的单晶体管共基组态放大器为交流变换单元,将交流输入电压变换为交流电流分量.一对匹配的精密恒流源电路分别为两个交流变换单元提供恒流偏置.将两个交流变换单元的输出电流叠加,抵消偏置电流,即可获得无偏置交流电流.该电路利用运放获得优异的直流性能,但运放位于交流回路之外.交流信号回路中只有晶体管和无源元件,从而同时实现了良好的噪声性能和高频性能.     

低误差开关电流存储单元

详细分析了限制开关电流(SI)精度的主要误差,在共源-共栅组态存储单元的基础上,根据在开关晶体管关断前消除反型层可以改善电荷注入误差的原理,提出一种新型低误差开关电流存储单元.其主要思想是通过消除开关晶体管沟道内的可动电荷、降低存储单元的输出电导,以改善电荷注入误差和电导比误差.采用TSMC 0.25μtm CMOS模型参数进行HSPICE仿真,结果表明,该结构能够很好地降低电路误差,提高开关电流电路的精度.     

基于衬底运放的2阶温度补偿带隙基准电路

采用TSMC 0.25μm CMOS工艺,提出了一种基于衬底驱动放大器的高精度带隙基准(BGR)电路。采用衬底驱动技术的放大器,有效地降低了电源电压;通过PTAT2电流产生电路对基准电路进行2阶温度补偿,有效地降低了输出基准电压的温度系数;采用改进型共源共栅输出级电路,很好地改善了电路的电源抑制比(PSRR)。HSPICE仿真结果显示:在2 V供电电压下,输出基准电压为1.261 V,温度系数为8.24×10-6/℃,低频电源抑制比-为91 dB。整体电路功耗为1.37 mW。