Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.     

Computer‐aided design methodology for linearity enhancement of multiwatt GaN HEMT amplifiers using multiple parallel devices

This article presents a design methodology for linearizing GaN HEMT amplifiers based on splitting a large FET into multiple parallel FETs with same total gate periphery and by biasing them individually. By varying the biases, the magnitude and the phase of the IMD3 components at the output of FET changes. A detailed simulation methodology using commercial microwave CAD software is presented. Simulation results show that by biasing one device in Class AB and other(s) in deep Class AB mode, IMD3 components of parallel FETs can be made out of phase to each other leading to cancellation and improvement in linearity. Three prototype circuits were simulated using (a) a single 5 mm FET (1 × 5 mm), (b) two parallel 2.5 mm FETs (2 × 2.5 mm), and (c) four parallel 1.25 mm FETs (4 × 1.25 mm), for a total gate periphery of 5 mm, over the frequency range of 0.8 to 1.0 GHz. IMD3 improvement up to 20 dBc was achieved with the 4 × 1.25 mm circuit when the FET biases were optimized. Measurement results show improvement in linearity up to 20 dBc for 4 × 1.25 mm circuit. The proposed method improves linearity without a substantial penalty on the power consumption and is straightforward to implement.     

Optimal design of Raman fibre amplifier based on terminal value optimization strategy and shuffled frog leaping algorithm

This paper introduces an evolutionary algorithm, Shuffled Frog Leaping Algorithm (SFLA), to solve the optimization problem in designing the multi-pumped Raman Fibre Amplifier (RFA). SFLA is a powerful optimizer tool because of its efficient mathematical expressions and global search capability. We utilize SFLA to determine the optimal pump wavelengths and pump powers by minimizing the gain ripple of RFA. To accelerate calculations, a terminal value optimization strategy (TVOS) is incorporated into the evolution of SFLA. This proposed strategy takes the terminal power values of pumps as the decision variables in optimization. Then, the optimal original power values of the pumps are obtained by solving the Power Coupled Equations once, without using the traditional method of repetitive guesses.The combination of SFLA and TVOS enhances the efficiency of optimization and accelerates calculation, while satisfying the design requirements of RFA.The simulation results show that nearly 65% of computational time has been saved compared with the traditional average power analysis. The 4-pumped C+L band of backward multi-pumped RFA with the average net gain of 0 dB, 1 dB and 2 dB are designed individually, where the gain ripple is less than 0.64 dB. The combination of SFLA and TVOS enhance the optimization efficiency and improve the performance of RFA with good gain profile.     

GaN中质子辐照损伤的分子动力学模拟研究

本文利用分子动力学方法研究了GaN在质子辐照下的损伤。对不同能量（1~10 keV）初级离位原子（PKA）引起的级联碰撞进行了研究，分析了点缺陷与PKA能量的关系、点缺陷随时间的演化规律、点缺陷的空间分布及点缺陷团簇的尺寸特征。研究结果表明，点缺陷的产生与PKA能量呈线性关系，不同类型的点缺陷随时间演化规律相似，点缺陷多产生在PKA径迹旁，点缺陷团簇多为孤立的点缺陷和小团簇。     

应用于车载激光雷达的宽带AGC跨阻放大器

针对车载激光雷达接收端脉冲信号脉宽窄、动态范围大等特点,提出了一种新型宽带、宽动态范围和高增益的自动增益控制(AGC)跨阻放大器。采用改进型调节型共源共栅结构作为输入级,拓展了带宽。使用改进型吉尔伯特单元作为可变增益放大器,进一步提高了带宽和增益。增加了AGC环路,提高了输入动态范围。基于标准 0.18 μm CMOS工艺进行设计与仿真,整体版图尺寸为760 μm×650 μm。仿真结果表明,该电路的-3 dB带宽为1.06 GHz,跨阻增益为80.79 dBΩ,输入动态范围为60 dB(1 μA~1 mA),功耗为47.6 mW,满足车载激光雷达接收机的要求。     

Low-threshold lasing in a plasmonic laser using nanoplate InGaN/GaN

Plasmonic nanolaser as a new type of ultra-small laser,has gain wide interests due to its breaking diffraction limit of light and fast carrier dynamics characters.Normally,the main problem that need to be solved for plasmonic nanolaser is high loss induced by optical and ohmic losses,which leads to the low quality factor.In this work,InGaN/GaN nanoplate plasmonic nanolaser with large interface area were designed and fabricated,where the overlap between SPs and excitons can be en-hanced.The lasing threshold is calculated to be ～6.36 kW/cm2,where the full width at half maximum (FWHM) drops from 27 to 4 nm.And the fast decay time at 502 nm (sharp peak of stimulated lasing) is estimated to be 0.42 ns.Enhanced lasing charac-ters are mainly attributed to the strong confinement of electromagnetic wave in the low refractive index material,which im-prove the near field coupling between SPs and excitons.Such plasmonic laser should be useful in data storage applications,bio-logical application,light communication,especially for optoelectronic devices integrated into a system on a chip.     

An Integrated Flexible All-Nanowire Infrared Sensing System with Record Photosensitivity

Infrared (IR) photodetectors are a key optoelectronic device and have thus attracted considerable research attention in recent years. Photosensitivity is an increasingly important device performance parameter for nanoscale photodetectors and image sensors, as it determines the ultimate imaging quality and contrast. However, photosensitivities of state-of-the-art low-dimensional nanostructure-based IR detectors are considerably low, limiting their practical applications. Herein, a biomimetic IR detection amplification (IRDA) system that boosts photosensitivity by several orders of magnitude by introducting nanowire field effect transistors (FETs), resulting in a peak photosensitivity of 7.6 × 10⁴ under an illumination of 1342 nm, is presented. Consequently, high-contrast imaging of IR light is obtained on the flexible IRDA arrays. The image information can be then trained and recognized by an artificial neural network for higher image-recognition efficiency. This work provides a new perspective for developing high-performance IR imaging systems, and is expected to undoubtedly enlighten future work on artificial intelligence and biorobotic systems.     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².