LMI searches for anticausal and noncausal rational Zames–Falb multipliers

Given a linear time-invariant plant, the search for a suitable multiplier over the class of Zames–Falb multipliers is a challenging problem which has been studied for several decades. Recently, a new linear matrix inequality search has been proposed over rational and causal Zames–Falb multipliers. This letter analyzes the conservatism of the restriction to causality on the multipliers and presents a complementary search for rational and anticausal multipliers. The addition of a Popov multiplier to the anticausal Zames–Falb multiplier is implemented by analogy with the causal search. As a result, a search over a noncausal subset of Zames–Falb multipliers is obtained. A comparison between all the search methods proposed in the literature is given.     

Regional Planning and Economic Development in the South West Region,Western Australia

Abstract

The paper examines the influence of a regional planning and development authority (the South West Development Authority) on economic growth in the South West Region of Western Australia. Employment and population changes are analysed along sectoral and spatial criteria. The findings show that between 1983 and 1989, the Authority's influence on the creation of employment opportunities was limited, being confined mostly to some gains in the public sector and to the promotion of the region and the city of Bunbury as tourist destinations. This ineffectiveness is associated with a lack of power to attract private and direct public investment to the region.     

适用于VLSI的一种并行乘法器结构

本文给出了二进制补码和无符号乘法器的通用表达式。对VLSI乘法器的结构进行了讨论。     

300吨连铸钢包下渣检测系统的研制

本文提出一种新颖的带有单线圈传感器的下渣检测系统，其传感器埋设在我国最大的３００吨连铸钢包包底的座砖中。该系统具有高的检测灵敏度，能对钢包浇注后期随钢水流出的熔渣作早期的检测与指示，在仅有少量熔渣开始流出的瞬间就能检测到下渣信号，随即关闭钢包滑动水口，终止浇注。这意味着可从每次钢包浇注中获得最大的钢产量，而进入中间包的渣量极少。系统经在线热试达到预期效果，能满足大吨位连铸生产的要求。     

升力式航天器再入最优轨迹研究

从无量纲飞行器质点运动方程出发，引入了能量参数对运动方程进行推导，使得运动方程和优化问题易于处理．通过将气动力假设为能量参数的分段连续线性函数。并且采用Runge-Kutta数值计算方法，将轨迹优化问题转化为多维非线性规划问题．应用广义乘子法对其进行数值求解．针对给定不同最大航迹角的2种情况，获得了总加热量最小，满足终端要求以及过载、动压、热流约束的最优轨迹，分析了返回最优轨迹的特点。     

一种用于32位CPU的CPL流水线乘加器的设计

综合的32位乘加器需采用5段流水线才能满足CPU的设计指标，但这样会造成与CPU指令流水线不匹配，带来了控制复杂化。为解决这个问题，采用互补传输门逻辑(CPL)设计了用于32位CPU的高速乘加器，使其流水线段数从原来的5段缩减为与CPU指令流水线相匹配的3段，简化了控制、降低了功耗、节省了面积。     

流水线阵列乘法器的功耗分析和优化

针对流水线结构阵列乘法器，分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析，创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。实验结果证明，这种优化方法能够带来明显的功耗节省。类似方法也可普遍用于逻辑行为对称但实现结构不对称的数据通路单元的低功耗设计实现中。     

一种双精度浮点乘法器的设计

设计了一个双精度浮点乘法器。该器件采用改进的BOOTH算法产生部分积，用阵列和树的混合结构实现对部分积的相加，同时，还采用了快速的四舍五入算法，以提高乘法器的性能。把设计的乘法器分为4级流水线，用FPGA进行了仿真验证，结果正确；并对FPGA实现的时序结果进行了分析。