结构函数法评估漏源电压对AlGaAs/InGaAs PHEMTs热阻的影响

本文通过实验测量和仿真研究了不同漏源电压对AlGaAs/InGaAs PHEMTs热阻的影响。结果表明,等功率下,热阻随着漏源电压的减小呈下降趋势,并且小电压大电流下热阻值最小。应用结构函数法可以分别提取出芯片级和封装级的热阻值。模拟结果表明,沟道中电场最强的地方出现在靠近漏一侧的栅边缘,相对较小的漏源电压产生的电场也较低,这就是导致等功率下热阻随漏源电压下降的原因。     

Evaluation of the drain-source voltage effect on AIGaAs/InGaAs PHEMTs thermal resistance by the structure function method

The effect of drain-source voltage on A1GaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that A1GaAs/InGaAs PHEMTs thermal resistance presents a downward trend under the same power dissipation when the drain-source voltage （VDs） is decreased. Moreover, the relatively low VDS and large drain-source current （IDs） result in a lower thermal resistance. The chip-level and package-level thermal resistance have been extracted by the structure function method. The simulation result indicated that the high electric field occurs at the gate contact where the temperature rise occurs. A relatively low VDS leads to a relatively low electric field, which leads to the decline of the thermal resistance.     

Power performance and scalability study of AlGaAs/GaAs double-recessed pseudomorphic high electron mobility transistors on unthinned substrate for coplanar waveguide circuit applications

We have investigated the power performance and scalability of AlGaAs/GaAs Double-Recessed Pseudomorphic High Electron Mobility Transistors (DR-PHEMTs) at 10 GHz on an unthinned GaAs substrate for CoPlanar Waveguide (CPW) circuit applications. It was found that the output power varied linearly with the logarithm of the device’s gate width ranging from 200 to 1000 μm. It increased at a rate of 0.01 dB/μm. That worked out to a doubling of output power (or 3 dB) for every 300 μm increase in the gate width. Gain decreased at a rate of about 0.005 dB/μm while PAE generally improved when the gate width was increased. As for DC measurement, the maximum transconductance of the device was about 375 mS/mm at V_G = −0.5 V and V_DS = 3 V. The gate-drain breakdown voltage (BV_GD) measured was −20 V, defined at I_G = −1 mA/mm. The microwave performance of the devices was measured on-wafer using a load-pull system at a bias of V_G = −0.5 V and V_DS = 8 V. For a device with a gate width of 1 mm, its saturated CW output power, gain and PAE value at 10 GHz was 27.5 dBm (0.55 W), 8 dB and 48%, respectively. At this same set of bias conditions, the value of f_t and f_max was 40 and 80 GHz, respectively.     

InAlAs/InGaAs PHEMTs的设计及其110GHz全频段小信号建模

90-nm T-shaped gate InP-based In_0.52Al_0.48As/In_0.6Ga_0.4As pseudomorphic high electron mobility transistors were designed and fabricated with a gate-width of 2×30 μm,a source-drain space of 2.5 μm,and a source-gate space of 0.75 μm.DC,RF and small-signal model characterizations were demonstrated.The maximum saturation current density was measured to be 755 mA/mm biased at V_gs=0.6 V and V_ds=1.5 V.The maximum extrinsic transconductance was measured to be 1006 mS/mm biased at V_ds=—0.1V and V_ds=1.5 V.The extrapolated current gain cutoff frequency and maximum oscillation frequency based on S-parameters measured from 0.5 to 110 GHz were 180 and 264 GHz,respectively.The inflection point（the stability factor k=1）where the slope from-10 dB/decade（MSG） to-20 dB/decade（MAG） was measured to be 83 GHz.The smallsignal model of this device was also established,and the S-parameters of the model are consistent with those measured from 0.5-110 GHz.     

用于太赫兹InP基PHEMTs 1~110GHz全频段在片测试的系统校准方法的对比研究

本文分别采用Multiline-TRL (Thru-Reflect-Line)和LRM (Line-Reflect-Match) 在片系统校准方法,与传统的SOLT (Short-Open-Load-Thru) 校准方法在InP基PHEMTs片上S参数测试方面进行定量的对比。首次在70 KHz~110 GHz全频段实现一次校准,减小了传统的分段测试多次校准带来的系统误差,校准更加方便简单。对比结果表明,基于Multiline-TRL校准和LRM校准后测量的S参数一致,且均优于传统的SOLT校准方法,尤其是在高频段结果更加准确。首次基于拐点进行外推,且器件展现了优良的射频特性,包括最大电流增益截止频率ft= 247 GHz,最大振荡频率fmax= 392 GHz,其准确度高于传统的基于无拐点进行的外推。首次基于LRM校准测得器件的1~110 GHz全频段S参数,建立了器件的1~110 GHz全频段小信号模型,而非基于传统的通过低频测试数据外推获得。     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

一种在砷化镓上形成欧姆接触的新型六层金属系统

研究了在砷化镓上欧姆接触形成机理,并提出了一种新型的欧姆接触六层金属系统(Ni/Ge/Au/Ge/Ni/Au).在n型GaAs样品上实验了在380～460℃合金温度和50～120 s合金时间下形成欧姆接触,在400℃、60 s下典型的欧姆接触值为2.1x10-7Ω·cm2,同时合金后表面形貌光滑、平整.     

太赫兹InP基InAlAs/InGaAs PHEMTs的研制

研制了一种T型栅长为90 nm的InP基In0.52Al0.48As/In0.65Ga0.35As赝配高电子迁移率晶体管(PHEMTs).该器件的总栅宽为2×25 μm,展现了极好的DC直流和RF射频特性,其最大饱和电流密度和最大有效跨导分别为894 mA/mm和1640 mS/mm.采用LRM+ (Line-Reflect-Reflect -Match)校准方法实现系统在1~110 GHz全频段内一次性校准,减小了传统的分段测试多次校准带来的误差, 且测试数据的连续性较好.在国内完成了器件的1~110 GHz全频段在片测试,基于1~110 GHz在片测试的S参数外推获得的截止频率ft和最大振荡频率fmax分别为252 GHz和394 GHz.与传统的测试到40 GHz外推相比,本文外推获得的fmax更加准确.这些结果的获得是由于栅长的缩短,寄生效应的减小以及1~110 GHz全频段在片测试的实现.器件的欧姆接触电阻率减小为0.035 Ω·mm.     

InAlAs/InGaAs/InP基PHEMTs小信号建模及低噪声应用

利用改进的小信号模型对采用100nmInAlAs/InGaAs/InP工艺设计实现的PHEMTs器件进行建模, 并设计实现了一款W波段单片低噪声放大器进行信号模型的验证。为了进一步改善信号模型低频S参数拟合差的精度, 该小信号模型考虑了栅源和栅漏二极管微分电阻, 在等效电路拓扑中分别用Rfs和Rfd表示.为了验证模型的可行性, 基于该信号模型研制了W波段低噪声放大器单片.在片测试结果表明:最大小信号增益为14.4dB@92.5GHz, 3dB带宽为25GHz@85-110GHz.而且, 该放大器也表现出了良好的噪声特性, 在88GHz处噪声系数为4.1dB, 相关增益为13.8dB.与同频段其他芯片相比, 该放大器单片具有宽3dB带宽和高的单级增益.