Investigation of corrosion properties with Ni–P/TiNO coating on aluminum alloy bipolar plates in proton exchange membrane fuel cell

Aluminum alloy bipolar plates have unique application potential in proton exchange membrane fuel cell (PEMFC) due to the characteristics of lightweight and low cost. However, extreme susceptibility to corrosion in PEMFC operation condition limits the application. To promote the corrosion resistance of aluminum alloy bipolar plates, a Ni–P/TiNO coating was prepared by electroless plating and closed field unbalanced magnetron sputter ion plating (CFUMSIP) technology on the 6061 Al substrate. The research results show that Ni–P interlayer improves the deposition effect of TiNO outer layer and increase the content of TiN and TiO_xN_y phases. Compared to Ni–P and TiNO single-layer coatings, the Ni–P/TiNO coating samples exhibited the lowest current density value of (1.10 ± 0.02) × 10^?6 A·cm^?2 in simulated PEMFC cathode environment. Additionally, potential cyclic polarization measurements were carried out aiming to evaluate the durability of the aluminum alloy bipolar plate during the PEMFC start-up/shut-up process. The results illustrate that the Ni–P/TiNO coating samples exhibit excellent stability and corrosion resistance.     

Low voltage operating organic light emitting transistors with efficient charge blocking layer

Charge injection/blocking layers play important roles in the performances of organic electronic devices. Their incorporation into organic light emitting transistors has been limitted, due to generally high operating voltages (above 60 V) of these devices. In this work, two hole blocking molecules are integrated into tris-(8-hydroxyquinoline) aluminum (Alq₃) based light emitting transistors under operating voltage as low as 5 V. The effects of hole blocking and electron injection are decoupled through the differences in the energy levels. Significantly improved optical performance is achieved with the molecule of suitable energy level for electron injection. Surprisingly, a decreased performance is observed in the case of another hole blocking molecule evidencing that charge injection overweighs charge blocking in this device architecture.     

High-performance 2,9-DPh-DNTT organic thin-film transistor by weak epitaxy growth method

2,9-DPh-DNTT, an isomeric of diphenyl-dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b] thiophene (DPh-DNTTs), is an emerging candidate of high mobility organic semiconductor material. In this work, a high performance 2,9-DPh-DNTT organic thin-film transistor (OTFT) is fabricated by the method of weak epitaxy growth. The quality of 2,9-DPh-DNTT thin film was significantly improved when its epitaxial layer grows on an inducing layer of para-sexiphenyl (p-6P). Continuous large-area, highly ordered and terraced 2,9-DPh-DNTT polycrystalline thin films are obtained. The hole mobility of as-fabricated 2,9-DPh-DNTT thin-film transistor reaches up to 6.4 cm² V⁻¹s⁻¹. This simple process of preparing high mobility 2,9-DPh-DNTT thin-film transistor supplies a facile route of large-area OTFT fabrication.     

一种交直流混合输电系统直流侧双极故障保护策略

为进一步分析含柔性直流输电(MMC-HVDC)的交直流混合输电系统的故障特征,基于交直流混合输电系统和模块化多电平换流器(MMC)的拓扑结构,推导了MMC的数学模型,研究了直流系统双极短路的故障机理和故障特征,针对含MMC-HVDC的交直流混合输电系统的双极短路故障,设计了限流电路及闭锁换流站与交流断路器跳闸相结合的故障保护方案。以厦门市柔性直流输电系统为例,在PSCAD/EMTDC中搭建了交直流混合系统,并对保护方案进行了仿真验证。结果表明,提出的保护策略能有效地降低故障电流,提高系统稳定性。     

The effect of Cr doped in amorphous carbon films on electrical conductivity: Characterization and mechanism

Metallic bipolar plates (BPPs) are prospective candidates for BPPs in PEMFCs due to their lower cost and higher power density than traditional graphite. Coatings are used to enhance the electrical conductivity and anti-corrsive quality of BPPs, and amorphous carbon (a-C) films have attracted broad attentions from both industry and academia. In this study chromium was incorporated into a-C to further enhance conductivity. A series of Cr-doped a-C films (a-C:Cr) with different doping contents were prepared by CFUBMSIP. Moreover, Microstructure analyses and composition characterizations were performed to explore the mechanism. The results show that Cr decreases the interfacial resistance with satisfying the anti-corrosive behavior. XRD patterns indicate that Cr will form chromium carbide phase and pure metal phase. Moreover, TEM results also show that Cr atoms bond with C atoms. SEM photographs show that Cr atoms refine the grain size and compact the film all the same. C 1s spectrum of XPS shows that C-sp²/C-sp³ increases first and then decreases, reaching the maximum level of 1.708 at Cr_0.205, indicating the resistance drops first and then increases. In addition, Cr doping will also bring changes in nano-hardness and surface roughness.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

In-plane light emission of organic light-emitting transistors with bilayer structure using ambipolar semiconducting polymers

The concept of using an ambipolar bilayer semiconducting heterostructure in organic light-emitting transistors (OLETs) is introduced to provide a new approach to achieve surface emission. The properties of top-gate-type bilayer OLETs with ambipolar materials based on two types of fluorene-type polymers used as an emissive layer and an electron blocking layer are investigated. Line-shaped yellow–green emission occurs near a hole-injection electrode. When hole transport is dominant in the upper layer which acts as an electron blocking layer, and electrons are injected into the lower layer, an in-plane light-emitting pattern is observed. The measured in-plane emission zone confirms that both hole and electron transport are determined to occur mainly along the different organic layers between the source and drain electrodes, and an in-plane recombination zone of electrons and holes exists near the bilayer organic interface. This work is anticipated to be useful for the development of in-plane light-emitting transistors.     

THE effect of Srandom DOPANT fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.