Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

GLOBAL: A Design for Random Testability Algorithm

1MotivationsIncreasingdensityofVLSIchipsmakesthecostoftestingveryexpensive.Designfortestabilitycantemperthisproblemdrastically.Therearetwokindsofsolutions:(i)localsolutionl3'2]withlowcomputingcomplexity,whichcannotalwaysgetsatisfactoryresults;(ii)globa.lsolutionwithprohibitivecomputingcomplekityl1'5].T.H.Chen'andM.A.Breuer[1lpresentedanILPmodeltoplacetestpointsglobally.Becauseofitscomputingcomplealty,[1lcanonlydealwithsmallormediumscalecircuits.SCOAPisusedin[1],whichisnotaveryaccuratet…     

On GID-Testable Two-Dimensional Iterative Arrays

A new approach is presented for easily testable two-dimensional iterative arrays.It is an improvement of GI-testability (Group Identical testability)and is referred to as GID-testability (Group Identical and Different testability).In a GID-testable two-dimensional array,the primary x and y outputs are organized into groups and every group has more than one output.This is similar to the GI-testable arrays.However,GID-testability not only ensures that identical test responses can be obtained from every output in the same group when an array is fault free,but also ensures that at least one output has different test responses (from the other outputs in a group)when a cell in the array is faulty.Therefore,all faults can be detected under the assumption of a single faulty cell model.It is proved that an arbitrary two-dimensional iterative array is GID-testable if seven x-states and seven y-states are added to the original flow table of the basic cell of the array.GID-testability simplifies the response verification of built-in-self-testing in a way similar to PI-and GI-testability^[6-9].Therefore,it is suitable for BIST design.     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

基于多信号流模型的模型封装与解包技术

随着科技的快速发展,设备系统的复杂程度越来越高,多信号流模型是系统测试性分析的常用模型,为解决复杂系统建模分析时对其各分系统信息保密问题,提出了一种基于多信号流模型的模型封装与解包方法。该方法首先确定了封装模块数据信息并实现封装,然后构建封装模块测试信息描述表,描述了封装模块内部故障、内部测试与外部信息的关系以及封装模块本身对外部信息的影响,实现了模块的解包。实验表明,该描述方法可以有效地屏蔽了被封装的分系统模型的技术信息,有利于各分系统设计者之间的信息保密,同时利用该描述方法,还可以有效地减少测试性分析所需的时间。     

基于斜率特征的模拟电路故障诊断新方法

针对低可测性模拟电路存在的模糊组问题,提出一种模拟电路故障诊断新方法。利用不同元件在电路可及节点间的斜率特征关系建立斜率测试矩阵,依据斜率测试矩阵准确找到电路中存在的模糊组和独立可测元件,从而确定可诊断集,然后利用支持向量机对故障进行诊断。斜率法优点在于不需要对电路拓扑结构进行分析,计算简便,支持向量机结构简单,泛化能力强。实验表明该方法具有良好的模拟电路故障诊断效果。     

基于信息论的软件测试性分析方法的改进研究

随着软件产业的不断发展,软件不断向系统化、集成化发展,软件所实现的功能越来越强大,复杂程度越来越高,最终导致软件质量越来越难以保证。软件测试性分析能够提供软件测试性信息,通过这些信息设计人员能在设计和测试执行之前确定测试的难易程度和所需资源,从而决定是否需要修改设计以得到一个更易测试的软件。以信息论软件测试性分析方法为基础,将程序转化为信息转换图进而利用信息论的方法进行测试性分析,最后引入模糊综合评价的方法对分析结果进行评价,并通过实例对该方法的有效性进行验证。     

可测试性在光电雷达检测设备中的应用

简要分析了某型飞机光电雷达的工作过程,给出了基于虚拟仪器技术的光电雷达综合参数检测设备的软、硬件设计,重点阐述了可测试性设计在系统设计中的一般过程,以及在本设备中的应用.机内测试技术(B IT)在本设备中的应用,使设备内部具备检测和隔离故障的自动测试能力,从而有效地提高研制设备的可维修性、可用性、可靠性.     

多故障的电子设备系统诊断设计方法研究

针对复杂电子设备在使用过程中多故障诊断难的问题,以相关性模型为基础,提出了一种多故障诊断的设计方法;首先,根据相关性模型确定测试D矩阵,并获得组成单元与测试次数的关系矩阵;其次,根据每次实际测试的结果构建测试结果矩阵,并计算获得测试故障单元矩阵;最后,通过综合测试故障单元矩阵与测试次数关系矩阵的数据,确定故障单元的概率,根据故障概率定位出故障单元;通过实例验算表明:多故障诊断方法可准确定位故障单元,大幅降低误修率。     

机载显控设备测试性设计

机载显控设备作为人机交互终端,具有数据处理及与人交互的工作特点,采用传统BIT(机内测试)测试性设计方法,故障检测率指标难以满足用户要求;根据其设备组成和主要功能,结合FMECA(失效模式影响及危害度分析)分析结果,提出BIT检测与人工检测相结合的方式开展测试性设计,通过TADS软件建立设备测试性模型并进行了计算和分析,设备故障检测率由74.72%有效提高到93.26%,以较小代价实现了用户要求;为其他人机交互机载设备测试性设计提供参考,具有较好的工程实用价值。