Digital Microfluidics for Manipulation and Analysis of a Single Cell

The basic structural and functional unit of a living organism is a single cell. To understand the variability and to improve the biomedical requirement of a single cell, its analysis has become a key technique in biological and biomedical research. With a physical boundary of microchannels and microstructures, single cells are efficiently captured and analyzed, whereas electric forces sort and position single cells. Various microfluidic techniques have been exploited to manipulate single cells through hydrodynamic and electric forces. Digital microfluidics (DMF), the manipulation of individual droplets holding minute reagents and cells of interest by electric forces, has received more attention recently. Because of ease of fabrication, compactness and prospective automation, DMF has become a powerful approach for biological application. We review recent developments of various microfluidic chips for analysis of a single cell and for efficient genetic screening. In addition, perspectives to develop analysis of single cells based on DMF and emerging functionality with high throughput are discussed.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

一种智能型的PCB产业需求预测方法

目前需求预测在整个印制电路板产业的生产活动控制中正扮演着越来越重要的角色。分析了影响印制电路板需求的因素和现有的预测方法,提出了一种适用于PCB产业需求预测的有效方法——遗传/BP—神经网络。实验表明该方法能够进一步改善印制电路板预测的准确度和减少生产成本的消耗。     

高速印制电路板设计中的串扰问题和抑制

本文剖析了在高速PCB板级设计中信号完整性分析领域信号串扰的产生机制,并利用HyperLynx软件包仿真,结合工作中的实践,提出了相应的解决方案.     

微流控分析芯片制作中的低温键合技术

微流控分析芯片制作方法的研究是微流控分析的基础。制作性能良好的微流控分析芯片时,基片与盖片的键合技术十分重要。本文针对近年来发展迅速的低温键合技术,对各种方法进行了评价,并对其发展前景进行了展望。     

微波陶瓷基印制板制造工艺性研究

对微波陶瓷基印制板的制造工艺流程进行了简单的介绍,对所采用的工艺技术的有效性进行了较为详细的论述。     

The influence of plastic properties on chip formation

A two-dimensional finite-element model of the chip formation process is used to study the influence of the material law determining plastic flow on chip formation of titanium alloys at high cutting speeds. For simplicity, friction and thermo-mechanical properties of the tool are neglected in the simulations. Titanium chips are strongly segmented and therefore especially suitable to study the role of segmentation for the cutting force and other cutting parameters. Of special interest is the influence of the thermal softening parameter in the material law. Increasing thermal softening leads to a drastic decrease in the cutting force and a corresponding increase in chip segmentation. A variation of the hardening exponent is also performed. It is shown that the simulation results can be understood by using adiabatic flow stress curves. The variation of the hardening exponent leads to strongly differing chip shapes, although the cutting force stays nearly constant. This shows that mean cutting forces should not be used as simulation verification parameters.     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

浅谈酶在非接触印刷废纸脱墨中的应用

简要地介绍了纤维素酶、半纤维素酶和淀粉酶在非接触印刷废纸脱墨中的研究及其应用     

时钟电路的电磁兼容性设计

对时钟电路设计中的3个主要问题：阻抗、传输延迟以及容性负载分别进行了阐述、分析与计算，得出了能够改善时钟电路电磁兼容性（EMC）的设计方法，并通过实践得以证实。