Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Unsupervised noise-robust feature extraction for aerial image classification

The rich data provided by satellites and unmanned aerial vehicles bring opportunities to directly model aerial image features by extracting their spatial and structural patterns. Although convolutional autoencoders(CAEs) have been attained a remarkable performance in ideal aerial image feature extraction, they are still challenging to extract information from noisy images which are generated from capture and transmission. In this paper, a novel CAE-based noise-robust unsupervised learning method is proposed for extracting high-level features accurately from aerial images and mitigating the effect of noise. Different from conventional CAEs, the proposed method introduces the noise-robust module between the encoder and the decoder. Besides,several pooling layers in CAEs are replaced by convolutional layers with stride=2. The performance of feature extraction is evaluated by the prediction accuracy and the accuracy loss in image classification experiments. A 5-classes aerial optical scene and a 9-classes hyperspectral image(HSI) data set are utilized for optical image and HSI feature extraction, respectively. Highlevel features extracted from aerial images are utilized for image classification by a linear support vector machine(SVM)classifier. Experimental results indicate that the proposed method improves the classification accuracy for noisy images(Gaussian noise 2D σ=0.1, 3D σ=60) in both optical images(2D 87.5%) and HSIs(3D 85.6%) compared with the traditional CAE(2D 78.6%, 3D 84.2%). The accuracy loss in classification experiments increases with the increment of noise. Compared with the traditional CAE(2D 15.7%, 3D 11.8%), the proposed method shows the lower classification accuracy loss in experiments(2D 0.3%, 3D 6.3%). The proposed unsupervised noise-robust feature extraction method attains desirable classification accuracy in ideal input and enhances the feature extraction capability from noisy input.     

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.     

高正确率的双语语块对齐算法研究

高质量的自动对齐双语语块,对于机器翻译系统,特别是计算机辅助翻译系统的性能提高有重要作用,而且对于人工翻译以及辞典编纂也都有巨大的应用价值。该文提出基于单词间粘合度与松弛度的语块划分评分方法以及双语语块划分的双向约束算法,使得源语言和目标语言的语块的划分与对齐能相互促进。与传统方法相比,因为无需事先进行双语语块划分,而是在搜索最佳对齐时动态地考察划分效果,故可以减少边界划分错误对对齐结果的影响。该算法获得了远超过传统算法的高正确率。     

On designing endurance aware erasure code for SSD-based storage systems

Erasure codes are applied in both HDD and SSD storage systems to improve the reliability. The design of erasure codes for SSD-based systems should be performed with respect to a specific feature of SSDs, i.e., endurance. Endurance is defined as the number of Program/Erase (P/E)-cycles that one SSD can endure for reliable operation. The common metric for comparing the endurance of two systems is the number of P/E-cycles, which is yielded by time-consuming simulations. This paper proposes two new metrics called DPD-factor and GDP-pattern, for comparing the effect of erasure codes on the endurance of systems based on their encoding designs, without simulation. With respect to the endurance, EA-EO is designed as the modification of EVENODD with smaller DPD-factor. The endurance of EVENODD and EA-EO are compared regarding the system configurations: the size of stripe unit, the number of disks, and the sizes of request. The results of comparison show that the best configurations of system for enhanced endurance are: 1) a large number of disks are applied in systems, or 2) the size of request is equal to the stripe unit size. Furthermore, it concludes that a code with smaller DPD-factor and a sequential GDP-pattern can provide higher endurance for systems.     

Tolerating transient illegal turn faults in NoCs

Network-on-Chip (NoC) is becoming a competitive solution to connect hundreds of processing elements in modern computing platforms. Under the trend of shrinking feature sizes, circuits are likely to suffer from faults which lead to degraded performance and erroneous behaviour. Compared to permanent faults, transient faults happen even more frequently and seriously while they are hidden within complex on-chip behaviours. One of the serious consequences caused by transient faults is taking illegal turns by the packets after the damage of control logic in on-chip routers which may lead to a deadlock situation and eventually crashing the entire system. To avoid this situation, in this paper, we propose a comprehensive scheme called ODT including an improved router architecture, an illegal-turn-resilient routing algorithm, online fault-detect units and a fault classification method. By applying ODT, more turns are supported on routing level and the deadlock situations can be significantly reduced. Experimental results indicate up to 22% increase of the survived packets in the network when 4% of routing computation units in failure. The extra area overhead and power consumption of ODT method is around 9.22% and 9.63%.     

3D holoscopic image coding scheme using HEVC with Gaussian process regression

3D holoscopic image, also known as integral imaging, light field imaging and plenoptic imaging, can provide a natural and fatigue-free 3D visualization. However, a large amount of data is required to represent the 3D holoscopic content. Therefore, efficient coding schemes for such particular type of image are needed. In this paper, we propose a Gaussian process regression based prediction scheme to compress the 3D holoscopic image. In the proposed scheme, the coding block and its prediction supports are modeled as a Gaussian process (GP) and Gaussian process regression (GPR) is used to obtain a better prediction of the coding block. Limited searching windows in horizontal and vertical directions are used to obtain the prediction supports, and a filtration method is designed to judge the reliability of the obtained prediction supports. Moreover, in order to alleviate the high complexity caused by GPR, a sparsification method is also put forward. Experimental results demonstrate the advantage of the proposed scheme for 3D holoscopic image coding in terms of different quality metrics as well as the visual quality of the views rendered from decompressed 3D holoscopic content, compared to the HEVC intra-prediction method and several other prediction methods in this field.     

Stereoscopic view synthesis based on region-wise rendering and sparse representation

Depth image-based rendering (DIBR), which is used to render virtual views with a color image and the corresponding depth map, is one of the key techniques in the 2D to 3D conversion process. One of the main problems in DIBR is how to reduce holes that occur on the generated virtual view images. In this paper, we make two main contributions to deal with the problem. Firstly, a region-wise rendering framework, which divides the original image regions into three special classes and renders each with optimal adaptive process respectively, is introduced. Then, a novel sparse representation-based inpainting method, which can yield visually satisfactory results with less computational complexity for high quality 2D to 3D conversion, is proposed. Numerical experimental results demonstrate the good performance of the proposed methods.     

From Business Intelligence to semantic data stream management

The Semantic Web technologies are being increasingly used for exploiting relations between data. In addition, new tendencies of real-time systems, such as social networks, sensors, cameras or weather information, are continuously generating data. This implies that data and links between them are becoming extremely vast. Such huge quantity of data needs to be analyzed, processed, as well as stored if necessary. In this position paper, we will introduce recent work on Real-Time Business Intelligence combined with semantic data stream management. We will present underlying approaches such as continuous queries, data summarization and matching, and stream reasoning.