Safe design of high-performance embedded systems in an MDE framework

In this paper, we use the UML MARTE profile to model high-performance embedded systems (HPES) in the GASPARD2 framework. We address the design correctness issue on the UML model by using the formal validation tools associated with synchronous languages, i.e., the SIGALI model checker, etc. This modeling and validation approach benefits from the advantages of UML as a standard, and from the number of validation tools built around synchronous languages. In our context, model transformations act as a bridge between UML and the chosen validation technologies. They are implemented according to a model-driven engineering approach. The modeling and validation are illustrated using the multimedia functionality of a new-generation cellular phone.     

Clock constraint specification language: specifying clock constraints with UML/MARTE

The Object Management Group (OMG) unified modeling language (UML) profile for modeling and analysis of real-time and embedded systems (MARTE) aims at using the general-purpose modeling language UML in the domain of real-time and embedded (RTE) systems. To achieve this goal, it is absolutely required to introduce inside the mainly untimed UML an unambiguous time structure which MARTE model elements can rely on to build precise models amenable to formal analysis. The MARTE Time model has defined such a structure. We have also defined a non-normative concrete syntax called the clock constraint specification language (CCSL) to demonstrate what can be done based on this structure. This paper gives a brief overview of this syntax and its formal semantics, and shows how existing UML model elements can be used to apply this syntax in a graphical way and benefit from the semantics.     

UML活动图到时间Petri网的映射方法

UML被广泛应用于嵌入式实时系统等领域的建模,而嵌入式实时系统对时间响应的要求非常严格,UML缺乏对系统时间约束的描述和形式化语义。因此,提出了一种结合MARTE与UML带有时间约束的UML活动图模型,并定义相应的映射规则,将该活动图模型映射到时间Petri 网模型,最后通过实例验证了该映射方法的正确性和实用性。     

模型驱动的嵌入式系统设计安全性验证方法研究

基于模型的嵌入式系统安全性分析与验证方法是近年来在安全攸关系统工程领域中出现的一个重要研究热点。提出一种基于模型驱动架构的面向SysML/MARTE状态机的系统安全性验证方法,具体包括:构建了具备SysML/MARTE扩展语义的状态机元模型,以及安全性建模与分析语言AltaRica的语义模型GTS的元模型;然后建立了从SysML/MARTE状态机模型分别到时间自动机模型以及AltaRica模型的语义映射模型转换规则,并基于AMMA平台和时间自动机验证工具UPPAAL设计实现了对SysML/MARTE状态机的模型转换与系统安全性形式化验证的框架。最后给出了一个飞机着陆控制系统设计模型的安全性验证实例分析。     

Foundations of a new software engineering method for real-time systems

The design of a fault-tolerant distributed, real-time, embedded system with safety-critical concerns requires the use of formal languages. In this paper, we present the foundations of a new software engineering method for real-time systems that enables the integration of semiformal and formal notations. This new software engineering method is mostly based upon the ”COntinuuM” co-modeling methodology that we have used to integrate architecture models of real-time systems (Perseil and Pautet in 12th International conference on engineering of complex computer systems, ICECCS, IEEE Computer Society, Auckland, pp 371–376, 2007) (so we call it “Method C”), and a model-driven development process (ISBN 978-0-387-39361-2 in: From model-driven design to resource management for distributed embedded systems, Springer, chap. MDE benefits for distributed, real time and embedded systems, 2006). The method will be tested in the design and development of integrated modular avionics (IMA) frameworks, with DO178, DO254, DO297, and MILS-CC requirements.     

从UML到GSPN的转换和性能分析方法

UML模型一般不能直接进行性能分析,需要利用模型转换的方法将其转换成其他分析模型,比如排队论、随机进程代数或者随机Petri网等模型。利用Eclipse平台上的Papyrus建立3种类型的UML模型(用例图、部署图和活动图)来对系统进行建模,并利用MARTE规范添加一些性能相关的信息;然后利用ATL实现UML模型到广义随机Petri网(GSPN)模型的转换,并使用XStream将上一步得到的GSPN模型转换成分析工具所支持的格式;最后利用基于GSPN的性能分析方法进行系统性能分析。同时给出了一系列性能指标的计算方法,如利用率、吞吐量、平均等待请求的数目以及响应时间等,可以考察系统性能的多个方面,方便系统设计和开发人员对系统性能进行分析和优化。     

基于MDA的实时软件资源建模与模型转换的方法

模型驱动体系结构(MDA)是一种以模型为中心的软件开发框架,其本质是元建模与模型转换。提出了一种基于MDA的实时软件资源建模与模型转换的方法。首先通过元建模抽象出包含资源信息的MARTS元模型以及价格时间自动机的元模型;然后利用模型转换语言ATL对MARTS元模型和价格时间自动机元模型构造转换规则,通过将对应的实例模型进行相互转换,实现在MDA下MAR"I'E模型到价格时间自动机模型的转换;最后通过形式化工具UPPAAL对模型转换结果进行形式化验证。实例分析表明了该方法的可行性与有效性,它能够提高实时软件资源建模的可信性。     

Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation

The proposed approach presents a method for automatically synthesizing the SW code of complex embedded systems from a model-driven system specification. The solution is oriented to enabling easy exploration and design of different allocations of SW components in heterogeneous platforms, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. The consequent communication overhead reduction can result in an important advantage for system performance optimization.     

基于UML MARTE处理AADL的端到端流延迟

AADL和MARTE都支持对实时嵌入式系统形式化建模的分析。利用MARTE的时间模型设备,研究MARTE是如何对实时嵌入式系统的建模和分析的,能够比较准确的通过事件或者数据端口的端到端流延迟分析,表达AADL周期性或非周期性任务。     

带数据约束实时系统的模型检测

带数据约束的实时系统是指一种既带有时间约束又带有数据变量约束的计算系统。目前将离散数据约束和连续时间约束统一在一个模型中的规范及验证研究较少。文中提出了一种既带有连续数据约束又带有离散数据约束的规范——基于连续时间的ZIA规范,并给出它的时序逻辑。MARTE是UML在嵌入式实时系统领域的建模规范,在工业界的应用非常广泛,但是目前对其模型检测的研究较少。在MARTE的基础上扩展Z,提出了Z-MARTE,并将Z-MARTE转换为基于连续时间的ZIA模型,在实现对连续时间ZIA模型检测的同时,也实现了对Z-MARTE的模型检测。最后通过一个实例进行验证,说明此方法可行有效。