首页 | 本学科首页   官方微博 | 高级检索  
文章检索
  按 检索   检索词:      
出版年份:   被引次数:   他引次数: 提示:输入*表示无穷大
  收费全文   18篇
  免费   0篇
  国内免费   1篇
电工技术   2篇
能源动力   9篇
石油天然气   1篇
无线电   4篇
原子能技术   1篇
自动化技术   2篇
  2022年   1篇
  2021年   1篇
  2020年   3篇
  2018年   1篇
  2017年   3篇
  2014年   1篇
  2013年   2篇
  2012年   1篇
  2011年   2篇
  2010年   1篇
  2009年   1篇
  2004年   1篇
  2001年   1篇
排序方式: 共有19条查询结果,搜索用时 15 毫秒
1.
A semi-empirical non-isothermal model incorporating coupled momentum, heat and mass transport phenomena for predicting the performance of a proton exchange membrane (PEM) water electrolysis cell operating without flow channels is presented. Model input parameters such as electro-kinetics properties and mean pore size of the porous transport layer (PTL) were determined by rotating disc electrode and capillary flow porometry, respectively. This is the first report of a semi-empirical fully coupled model which allows one to quantify and investigate the effect of the gas phase and bubble coverage on PEM cell performance up to very high current densities of about 5 A/cm2. The mass transport effects are discussed in terms of the operating conditions, design parameters and the microstructure of the PTL. The results show that, the operating temperature and pressure, and the inlet water flowrate and thickness of the PTL are the critical parameters for mitigating mass transport limitation at high current densities. The model presented here can serve as a tool for further development and scale-up effort in the area of PEM water electrolysis, and provide insight during the design stage.  相似文献   
2.
设计并制作了天光Ⅱ-B脉冲功率装置的电流电压诊断设备,根据天光Ⅱ-B脉冲功率装置的同轴传输线结构特点,在传输线末端设置了用于测量负载电压的电容分压器。利用金属膜连接传输线外筒与负载外筒构成回流来测量负载的电流,并利用电路模拟软件对此过程进行模拟,两个诊断探头采取直接标定的方法,测定电容分压器的分压比和回流器的灵敏度。实验结果表明,该探头性能稳定、时间响应快、功率负荷大,是测量脉冲电流与电压的一种理想工具。  相似文献   
3.
Binary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD‐based pass transistor logic (PTL) logic synthesis is presented for low‐power and high‐performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one‐to‐one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer‐based construction of PTL circuits, and less switching activities. Copyright © 2011 John Wiley & Sons, Ltd.  相似文献   
4.
This paper presents 2D thermal model of a fuel cell to elucidate some of the issues and important parameters with respect to temperature distributions in PEM fuel cells. A short review on various properties affecting the temperature profile and the heat production in the polymer electrolyte fuel cell is included. At an average current density of 1 A cm−2, it is found that the maximum temperature of the MEA is elevated by between 4.5 and 15 K compared to the polarisation plate temperature. The smallest deviation corresponds to one dimensional transport, while the largest corresponds to the two dimensional transport considering anisotropic thermal conductivity. The two dimensional thermal model further predicts increased lost work. While most of the heat generation is allocated in the cathode, it is shown that the heat effect may be balanced by the water phase change in the anode. The most significant factor in determining the temperature distribution is the gas channel geometry (width and channel type), followed by the thermal conductivity of the porous transport layer and state of the water in the cell.  相似文献   
5.
In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed circuits are area and power efficient because minimum-sized transistors are used in ratioless realisations. At the output, the designs give strong logic-levels. The topologies have minimised delay because the critical path consists of only three minimum-sized transistors. The delay estimation is presented. The circuits are simple and layouts are easy to build. Further, rail-to-rail voltage-swing at the output ensures good driving capability even at low voltages and at high frequencies ranging up to 10 GHz with minimum transistor count. The proposed designs and other existing candidate designs are simulated in a pragmatic condition on Cadence 90 nm CMOS technology at various supply voltages ranging from +0.8 V to +1.2 V. The simulation results illustrate that the proposed designs have comparable delay time to most candidate designs while it outperform all of them on total power consumption and PDP. As expected, the TG-based design reports best performance while the PT-based design follow as closed second with better component economy and control input overload. An application of the proposed XORs in ripple carry adders confirms the functionality of the cells in circuit implementation.  相似文献   
6.
Gas permeation through a membrane electrode assembly (MEA) is an important issue in the development of polymer electrolyte membrane (PEM) water electrolyzers, because it can cause explosions and efficiency losses. The influence of operating pressure, temperature and MEA modifications on the permeation was already investigated. However, most of the studies pay no attention to the compression of the porous transport layer (PTL) of the MEA when assembling it in a test cell to carry out the experiments.This paper deals with the impact of the PTL compression on hydrogen permeation and cell voltage. Polarization, impedance and permeation measurements are used to demonstrate that the compression significantly affects the MEA's properties. Measurements show either a linear or nonlinear correlation between current density and hydrogen permeation, depending on the compression.The results indicate that the compression of the PTL must be taken into account for developing MEAs and comparing different permeation measurements.  相似文献   
7.
Polymer electrolyte membrane (PEM) electrolyzers have received increasing attention for renewable hydrogen production through water splitting. In present work, a two-dimensional (2-D) multi-physics model is established for PEM electrolyzer to describe the two-phase flow, electron/proton transfer, mass transport, and water electrolysis kinetics with focus on the porous transport layer (PTL) and the channel-land structure. After comparing four sets of experimental data, the model is employed to investigate PTL thickness impact on liquid water saturation and local current density. It is found that the PTL under the land may have much lower liquid saturation than that under the channel due to land blockage. The PTL thickness may significantly impact liquid water access to the catalyst layer (CL) under the land. Specifically, the 100 μm thick PTL shows less than 1% liquid saturation at the CL-PTL interface under 4–5 A/cm2, leading to water starvation and electrolyzer voltage increase. As the operating current density decreases under 2–3.5 A/cm2, the liquid saturation recovers and increases to about 10–20%. In thicker PTLs, the liquid saturation is higher under the land reaching 30–40% at the CL-PTL interface under 5 A/cm2 for 200 and 500 μm thick PTLs. For the 100 μm thick PTL, the local current density drops to below 0.5 A/cm2 under the land with 5 A/cm2 average current density. For the 200 and 500 μm thick PTLs, the local current is almost uniform in the in-plane direction. The numerical model is extremely valuable to investigate PTL properties and dimensions to optimize channel-land design and configuration for high performing electrolyzers.  相似文献   
8.
The thermal conductivity and the thickness change with pressure of several different micro porous layers (MPL) used for the polymer electrolyte membrane fuel cell (PEMFC) were measured. The MPL were made with different compositions of carbon and polytetrafluoroethylene (PTFE). A one-dimensional thermal PEMFC model was used to estimate the impact that the MPL has on the temperature profiles though the PEMFC.  相似文献   
9.
Power consumption and performance are two important design constraints for logic synthesis in design automation. In this paper, we propose an efficient synthesis algorithm to minimize power dissipation and optimize performance of the given digital circuits by constructing a binary decision diagram (BDD) whose nodes can be implemented by CMOS logics and pass‐transistor logics (PTL) in a cell library. For BDD mapped circuits, the conventional synthesis algorithms need three cells: the CMOS cell, PTL cell, and CMOS remapping pattern. In the proposed synthesis algorithm, we first refine the cell library structure to two kinds of cells: PTL and CMOS cells. Next, a new algorithm is presented to select the suitable cells so that the areas and power dissipation can be decreased when the logic functions of the given digital circuits are mapped into BDD. The efficiency of this algorithm has been shown in the experimental results. Copyright © 2010 John Wiley & Sons, Ltd.  相似文献   
10.
This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.  相似文献   
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号