一种快速程序最坏执行时间分析方法研究

给出一种带有路径冲突检测的程序最坏情况执行时间估计方法,这种方法首先检测程序中存在的分支约束,然后将程序中存在的分支约束信息转化为程序流程控制图（CFG图）中结点之间的语义冲突,并按照结点对的形式保存在相应的冲突数组里,在接下来的WCET计算阶段通过边搜索程序执行路径边检测冲突数组里保存的已有的冲突关系以便在搜索路径的同时排除非可行执行路径,最终在可行执行路径集中选择具有最大执行时间的执行路径。与以往的方法相比,在保持估计精度的前提下,本文的方法避免了穷举所有执行路径带来的复杂度,提高了搜索的效率。实验结果表明本文方法对于语句间语义依赖关系比较强的实时程序能够快速且有效地给出估计结果。     

两种基于符号的最坏执行时间分析方法的比较与分析

通常的最坏执行时间分析方法只是得到一个常数,然后将这个常数应用在所有的地方,这将造成所得的值过于悲观（over pessimistic）.如果能以一个代数表达式代替,其中影响程序执行时间的一些未知值（如调用参数,运行平台参数等）都用参数来表示,然后在具体的环境中再根据具体的情况进行实例化,那么所获得的最坏执行时间将更加接近于实际的值.文章讨论了基于符号的最坏执行时间分析方法,分析了其特点,对两种基于符号的最坏执行时间分析方法进行了比较和研究,并给出了将来的研究方向.     

基于WCET分析的实时系统轨迹获取技术

时序约束是判断实时系统运行是否正确的重要规约.为了减小测试时由于对系统进行插装而产生的对实时系统行为的影响,提出了一种混合式监控方法.它对系统的时间干扰比纯软件方式小,并支持对系统的完全测试.此外,还提出一种基于WCET(worst-case execution time)分析技术的目标系统时间补偿方法,在精确地计算插入断言对目标系统的时间影响基础上,给出时间补偿.     

一种实时Java处理器''''区域''''内存实现模型

Java实时规范（RTSJ）提出的‘区域’内存（Scoped Memory）既避免了垃圾回收对系统实时性的影响，又能充分利用内存空间，引起了众多研究人员的重视．本文讨论了‘区域’内存的实现及影响最坏情况下执行时间（WCET）的因素，并提出一种针对嵌入式实时Java处理器的‘区域’内存实现模型．该模型中非实时处理在字节码被执行之前完成，消除了运行时管理‘区域’内存对WCET的影响，在简化处理器实现的同时保证了运行时WCET的可预测性．     

一种用于硬实时Java处理器的类转换器设计及实现

通过分析Class文件处理过程及其中影响实时性的操作，提出一种用于硬实时Java处理器的类转换器，它读取标准Class文件，处理并生成适合Java处理器直接执行的内存映像文件．由于装载、连接过程中大量操作（如符号引用的解析）都由类转换器提前处理完毕，使得Java处理器操作大为简化．同时，由于所有影响Java处理器实时性的操作也由类转换器提前处理，Java处理器最坏情况执行时间（Worst Case Execution Time）完全可预测．     

Improving WCET by applying worst-case path optimizations

It is advantageous to perform compiler optimizations that attempt to lower the worst-case execution time (WCET) of an embedded application since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been considerable effort to develop compiler optimizations to improve these paths in order to reduce the average-case execution time (ACET). In this paper, we describe an approach to reduce the WCET by adapting and applying optimizations designed for frequent paths to the worst-case (WC) paths in an application. Instead of profiling to find the frequent paths, our WCET path optimization uses feedback from a timing analyzer to detect the WC paths in a function. Since these path-based optimizations may increase code size, the subsequent effects on the WCET due to these optimizations are measured to ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate these WC path optimizations and present results showing the decrease in WCET versus the increase in code size. A preliminary version of this paper entitled “Improving WCET by optimizing worst-case paths” appeared in the 2005 Real-Time and Embedded Technology and Applications Symposium. Wankang Zhao received his PhD in Computer Science from Florida State University in 2005. He was an associate professor in Nanjin University of Post and Telecommunications. He is currently working for Datamaxx Corporation. William Kreahling received his PhD in Computer Science from Florida State University in 2005. He is currently an assistant professor in the Math and Computer Science department at Western Carolina University. His research interests include compilers, computer architecture and parallel computing. David Whalley received his PhD in CS from the University of Virginia in 1990. He is currently the E.P. Miles professor and chair of the Computer Science department at Florida State University. His research interests include low-level compiler optimizations, tools for supporting the development and maintenance of compilers, program performance evaluation tools, predicting execution time, computer architecture, and embedded systems. Some of the techniques that he developed for new compiler optimizations and diagnostic tools are currently being applied in industrial and academic compilers. His research is currently supported by the National Science Foundation. More information about his background and research can be found on his home page, http://www.cs.fsu.edu/∼whalley. Dr. Whalley is a member of the IEEE Computer Society and the Association for Computing Machinery. Chris Healy earned a PhD in computer science from Florida State University in 1999, and is currently an associate professor of computer science at Furman University. His research interests include static and parametric timing analysis, real-time and embedded systems, compilers and computer architecture. He is committed to research experiences for undergraduate students, and his work has been supported by funding from the National Science Foundation. He is a member of ACM and the IEEE Computer Society. Frank Mueller is an Associate Professor in Computer Science and a member of the Centers for Embedded Systems Research (CESR) and High Performance Simulations (CHiPS) at North Carolina State University. Previously, he held positions at Lawrence Livermore National Laboratory and Humboldt University Berlin, Germany. He received his Ph.D. from Florida State University in 1994. He has published papers in the areas of embedded and real-time systems, compilers and parallel and distributed systems. He is a founding member of the ACM SIGBED board and the steering committee chair of the ACM SIGPLAN LCTES conference. He is a member of the ACM, ACM SIGPLAN, ACM SIGBED and the IEEE Computer Society. He is a recipient of an NSF Career Award.     

用于优化WCET值的片上存储器分配方法

SPM(Scratchpad Memory)是实时嵌入式系统中常见的片上存储器,其分配管理在编译期进行,从而可以在编译完成时确定访存时延.当前的SPM分配方法主要用于减少程序在平均情况下的执行时间.然而,在硬实时系统中,最差情况下的执行时间(WCET, Worst-Case Execution Time)是更为关键的指标.通过分析优化程序WCET值过程中存在的主要问题以及现有算法,基于变量公用度概念,提出一种启发式搜索算法用于最小化程序WCET值的数据变量SPM分配,实验表明,论文提出的分配方法可获得更好的优化效果.     

信息物理系统实时任务WCET的研究

信息物理系统（CPS）是最近几年才出现的一个新的交叉领域的研究概念,它被普遍认为是计算机信息处理技术史上的下一次革命,将会改变人与现实物理世界之间的交互方式,具有广泛的应用前景。简要介绍了CPS的概念、一些新的特性。研究了CPS实时性方面的最坏执行时间（WCET）分析的组成部分、获取方法和计算算法,并比较了几种算法的优劣,列举了这一领域一些研究进展,讨论了WCET分析这一领域中存在的问题,给出了将来的研究方向。     

WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets

Determining a tight WCET of a block of code to be executed on a modern superscalar processor architecture is becoming ever more difficult due to the dynamic behaviour exhibited by current processors, which include dynamic scheduling features such as speculative and out-of-order execution in the context of multiple execution units with deep pipelines. We describe the use of Coloured Petri Nets (CP-nets) in a simulation based approach to this problem. A complex model of a generic processor architecture is described, with emphasis on the modelling strategy for obtaining the WCET and an analysis of the results.     

面向安全关键应用的多核处理器执行时间波动性分析

在安全关键系统中,针对多核处理器共享硬件资源竞争带来的执行时间波动性问题,提出了基于性能计数器PMR和RSB的通用测试方法,通过捕捉执行时间波动性相关的硬件事件来分析硬件资源的共享性、执行时间的波动性和硬件平台的黑盒或灰盒行为。此方法可用于硬件平台的性能评估,也可用于应用任务的资源消耗评估,从而为WCET预测提供指导。