Cognitive abilities,digital games and arithmetic performance enhancement: A study comparing the effects of a math game and paper exercises

Besides entertainment, games have shown to have the potential to impact a broader variety of cognitive abilities. Research has consistently shown that several aspects in cognition such as visual short-memory, multitasking and spatial skills can be enhanced by game play. In a previous study, it was found that playing Monkey Tales, a game aimed at training arithmetic skills, helped second grade pupils to increase their accuracy in mental calculation as compared to paper exercises. In this follow up study we explore whether traditional methods and game training differ in terms of the cognitive processes that both are able to impact. We incorporated standardized measures of working memory and visuo-motor skills. Additionally, the mathematics game was modified and its contents extracted to allow precise comparison between the gaming and paper exercises condition. Thus each single math exercise, type of question (e.g., multiple choice), quantity and order was perfectly matched in the game training and the traditional training conditions. Gains in arithmetical performance, and self-reported measures of enjoyment were also investigated. We found some evidence suggesting that arithmetic performance enhancement induced by game play and paper exercises differ not only in terms of enjoyment but also of working memory capacity improvements.     

基于三维胞元空间的MA双向并行路由算法

针对传统移动代理(MA)在监测无线传感器网络(WSNs)的感兴趣信息时产生的延迟较大和能耗较多问题,提出了基于三维胞元空间的MA双向并行(3D-BPMA)路由算法.3D-BPMA将MA与传统的客户/服务器(c/S)模式相结合,在胞元内利用C/S模式搜集信息,在单层胞元系统和路由器与路由器之间采用MA双向并行的策略进行传输.仿真结果表明:3D-BPMA与LCF,DSG-MIP算法相比减少了平均响应时间和网络平均能耗,提高了MA发送率.     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

嵌人式与独立存储器设计上的差异分析和研究

进入21世纪,随着集成电路的发展,SoC(System on Chip)片上系统应运而生。而作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重正逐步增加,并起着越来越重要的作用,那么嵌入式存储器与独立的存储器芯片在设计上存在着哪些差异?对此本文将以NOR型闪存为例在制造工艺的选取、衍生产品的设计、功耗与噪声、后端功能仿真、测试与修复等方面进行分析和研究。     

双转向垂向控缝技术实验研究及现场应用

针对压裂过程中缝高较难控制的问题，研制开发出新型的油溶性垂向双转向剂，并开展了室内实验研究。首次验证了转向剂对裂缝延伸的控制机理，确定了转向剂的适用浓度及控缝能力。实验表明，转向剂可以增加隔层应力3～4MPa左右。在此基础上研究了控制裂缝高度施工方案的设计方法，并利用全三维软件结合垂向应力剖面对控缝技术进行了优化。现场推广应用30井次，取得了较好的控缝效果。     

Context-Processing Deficits in Schizotypal Personality Disorder.

Research suggests that schizotypal personality disorder (SPD) is a part of the spectrum of schizophrenia-related illnesses. This article hypothesizes that a deficit in the representation and maintenance of context is a core cognitive disturbance in schizophrenia and that SPD individuals should demonstrate context-processing deficits. To test this hypothesis, the authors administered 3 versions of their AX-CPT task, designed to assess context processing, to 35 healthy controls and 26 individuals with DSM-IV SPD. They also administered working memory and selective attention tasks. SPD individuals displayed context representation deficits similar to those found in schizophrenia but did not show the same additional deficits in context maintenance. Context processing was strongly associated with working memory and selective attention performance in the SPD individuals. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Allocentric Versus Egocentric Spatial Memory After Unilateral Temporal Lobectomy in Humans.

Thirty patients who had undergone either a right or left unilateral temporal lobectomy (14 RTL; 16 LTL) and 16 control participants were tested on a computerized human analogue of the Morris Water Maze. The procedure was designed to compare allocentric and egocentric spatial memory. In the allocentric condition, participants searched for a target location on the screen, guided by object cues. Between trials, participants had to walk around the screen, which disrupted egocentric memory representation. In the egocentric condition, participants remained in the same position, but the object cues were shifted between searches to prevent them from using allocentric memory. Only the RTL group was impaired on the allocentric condition, and neither the LTL nor RTL group was impaired on additional tests of spatial working memory or spatial manipulation. The results support the notion that the right anterior temporal lobe stores long-term allocentric spatial memories. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.