Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

A register window scheduling method for prolog

Abstract

This paper describes a windowed register file management technique for Prolog that we call “SORWT'’ (Splittable Overlapped Register Window Technique). This scheme is implemented in our Prolog system. Two pointers, the CWP (Current Window Pointer) and TWP (Top Window Pointer), are used with the register file so that the environment, choice point and arguments can be stored in register windows. This greatly reduces the number of memory accesses and procedure call/return overhead. This paper describes in detail how Warren instructions can be implemented in a windowed register file system. A mapping function between register windows and memory window areas and register file overflow/underflow handling algorithms are also presented. In addition, to cope with argument overflow problems in a window, the concept of extended windows is proposed.

Thirty benchmark programs are used to study the following effects: performance issue of SORW versus conventional stacked register windows; optimal register file and window sizes; argument overflow rate; and the efficiency of extended windows.     

Syntax and semantics of universal programming languages

This paper deals with certain characterizations of the sets of positive integers which when represented as strings on a finite alphabet, form tree adjunct languages, As the context free languages constitute a subfamily of tree adjunct languages, the results carry over to the former as well.     

基于GCC的TMS320C67xx汇编代码的优化

为了使生成的汇编代码具有更高的执行效率,设计并实现了一种基于GCC的 TMS320C67xx汇编指令级的代码优化算法。首先,将汇编指令按照功能划分为不同的指令类型,并将汇编指令链接到链表中。然后,针对每一个寄存器建立对该寄存器的读写操作指令链表。最后,通过对指令类型的判断和对寄存器读写操作指令链表的分析,完成了冗余代码的删除和指令合并。实验结果表明,经过代码优化后,TMS320C67xx汇编代码的执行效率提高了20％左右,较中间代码级的优化算法执行效率提高了15％左右。     

A self‐applicable online partial evaluator for recursive flowchart languages

This paper describes a self‐applicable online partial evaluator for a flowchart language with recursive calls. Self‐application of the partial evaluator yields generating extensions that are as efficient as those reported in the literature for offline partial evaluation. This result is remarkable because it has been assumed that online partial evaluation techniques unavoidably lead to inefficient and overgeneralized generating extensions. The purpose of this paper is not to determine which kind of partial evaluation is better, but to show how the problem can be solved by recursive polyvariant specialization. The design of the self‐applicable online partial evaluator is based on a number of known techniques, but by combining them in a new way this result can be produced. The partial evaluator, its techniques, and its implementation are presented in full. Self‐application according to all three Futamura projections is demonstrated. The complete bootstrap of a compiler generator from a partial evaluator is also reported. Copyright © 2011 John Wiley & Sons, Ltd.     

Accurately Selecting Block Size at Runtime in Pipelined Parallel Programs

Loops that contain cross-processor data dependencies, known as DOACROSS loops, are often found in scientific programs. Efficiently parallelizing such loops is important yet nontrivial. One useful parallelization technique for DOACROSS loops is pipelining, where each processor (node) performs its computation in blocks; after each, it sends data to the next node in the pipeline. The amount of computation before sending a message is called the block size; its choice, although difficult to make statically, is important for efficient execution. This paper describes a flexible runtime approach to choosing the block size. Rather than rely on static estimation of workload, our system takes measurements during the first two iterations of a program and then uses the results to build an execution model and choose an appropriate block size which, unlike a static choice, may be nonuniform. To increase accuracy of the chosen block size, our execution model takes intra- and inter-node performance into account. It is important to note that our system finds an effective block size automatically, without experimentation that is necessary when using a statically chosen block size. Performance on a network of workstations shows that programs that use our runtime analysis outperform those that use static block sizes by as much as 18% when the workload is unbalanced. When the workload is balanced, competitive performance is achieved as long as the initial overhead is sufficiently amortized.     

Transformations for optimizing interprocess communication and synchronization mechanisms

This paper presents source-level transformations that improve the performance of programs using synchronous and asynchronous message passing primitives, including remote call to an active process (rendezvous). It also discusses the applicability of these transformations to shared memory and distributed environments. The transformations presented reduce the need for context switching, simplify the specific form of communication, and/or reduce the complexity of the given form of communication. One additional transformation actually increases the number of processes as well as the number of context switches to improve program performance. These transformations are shown to be generalizable. Results of hand-applying the transformations to SR programs indicate reductions in execution time exceeding 90% in many cases. The transformations also apply to many commonly occurring synchronization patterns and to other concurrent programming languages such as Ada and Concurrent C. The long term goal of this effort is to include such transformations as an otpimization step, performed automatically by a compiler.This work was supported by NSF under Grant Number CCR88-10617.     

Relations among Security Models for Authenticated Key Exchange

Usually, key‐establishment protocols are suggested in a security model. However, there exist several different security models in the literature defined by their respective security notions. In this paper, we study the relations between the security models of key establishment. For the chosen security models, we first show that some proven key‐establishment protocols are not secure in the more restricted security models. We then suggest two compilers by which we can convert a key‐establishment protocol that is secure in a specific security model into a key‐establishment protocol that is still secure in a more restricted security model.     

龙门式电火花线切割译码仿真程序设计

研究了龙门式电火花线切割译码仿真程序，构架了程序框架。对编译模块进行了细分，对仿真模块的层次结构及核心技术的实现做了详细介绍。介绍了二维工件、三维工件刀补的过程。     

基于PICC编译环境编写PIC单片机程序

Microchip公司生产的PIC系列单片机具有实用、低价、简单易学、低功耗、高速度、体积小、功能强等特点。体现了单片机发展的一种新趋势，而PICC具有许多特殊的性质。并且进行了C语言的扩展，从而可以更轻松地完成编程任务。本文简单介绍了PIC系列单片机在国内的发展情况，以Hi-Tech Software公司的Hi-Tech PICC编译器为例介绍了PICC和标准C的异同及Hi-Tech PICC语言的特点，详细介绍了PICC中的变量、指针、函数以及C与汇编混合编程的一些相关知识。并列举了许多例子以便读者理解。此外还着重介绍了用PICC开发PIC系列单片机时应注意的一些问题。