A comparison of manual handling risks in different domestic waste collection systems using three separate evaluation methods

Arising out of the challenge for Local Authorities (LAs) to operate sustainable systems of work, is to avoid the creation of ill-health including the most significant causes of physical absence, musculoskeletal disorders (MSDs).The study's aim was to compare the reliability of the manual handling element of the Health and Safety Executives (HSEs) risk comparator tool for different domestic waste collection methods with self-reported pain via body-mapping and MSD ill health absence rates. Participatory body-mapping exercises were carried out in five LAs with one LA resurveyed, six months after the move from 35 and 50 L containers to a wheeled bin recycling service.The lowest levels of self-reported pain were for services designed with 240l wheeled bins excluding glass; the highest levels were for services that included 100l of garden waste sacks and recycling boxes. Industry data supports previous laboratory studies showing wheeled bins to be associated with less MSD outcomes than boxes, baskets and sacks.Triangulation of data established a statistically significant correlation of 0.85 (Pearson) between average pain-count (APC) and the mean MSD absence rates, with a strong correlation of 0.77 (Spearman) between APC and risk rating. The correlation is moderate, 0.49 (Spearman) between MSD absence and risk rating, reflecting possible intervening variables and a low participation rate by LAs.The contribution of this study is to improve the design of sustainable waste collection strategies to minimise MSD associated absence. In the absence of reliable absence data, body mapping should be used as a proxy method of assessing MSD risk.     

适用于DC-DC开关电源的振荡器设计

应用于手机等通信电子产品电源系统的DC-DC开关电源变换器芯片,要求具有高性能的振荡器。鉴于此要求,设计了一款具有充放电电容的高性能振荡器。该振荡器基于0.5μm BCD工艺库,利用Cadence和Hspice软件,在芯片系统典型应用环境下仿真,得到的内同步振荡频率为794 k Hz,外部EN同步振荡频率为1 MHz到2MHz;在VCC=5.5 V,0~125℃温度范围内振荡器的频率偏移在6%以内。仿真结果显示,该振荡器性能良好,适用于DC-DC开关电源。     

Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization

This paper presents an efficient approach for the optimal designs of two analog circuits, namely complementary metal oxide semiconductor) two‐stage comparator with p‐channel metal oxide semiconductor input driver and n‐channel input and folded‐cascode operational amplifier using a recently proposed meta‐heuristic‐based optimization algorithm named as colliding bodies optimization (CBO). It is a multi‐agent algorithm that does not depend upon any internal control parameter, making the algorithm extremely simple. The main objective of this paper is to optimize the metal oxide semiconductor (MOS) transistors' sizes using CBO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. Simulation Program with Integrated Circuit Emphasis simulation has been carried out by using the optimal values of MOS transistors' sizes and other design parameters to validate that CBO‐based design is satisfying the desired specifications. Simulation results demonstrate that the design specifications are closely met and the required functionalities are achieved. The simulation results also confirm that the CBO‐based approach is superior to the other algorithms in terms of MOS area and performance parameters like gain, power dissipation, etc., for the examples considered. Copyright © 2016 John Wiley & Sons, Ltd.     

一种CNFET的多位三值比较器设计

As the ternary comparator faces problems of slow speed and high power consumption, this paper proposes a scheme for the magnitude ternary comparator of CNFET, which is researching on theory of multi-valued logic circuit and the structure of comparator circuit. First, the ternary decode signal is propagated to the comparator, then the encoder circuit encodes the results of comparison, and finally the magnitude ternary comparator is made up of all kinds of modules. The magnitude comparator is simulated by software, which demonstrates that it has a correct logic function, fast speed and low power consumption characteristics.     

基于平衡态的动态比较器失调电压分析和设计优化

本文提出了一种基于平衡态的动态比较器失调电压分析设计技术。以两支路电压电流相等的平衡态为分析基础,通过在复位电压跳变时刻引入补偿电压的方法,逐一分析了动态比较器各晶体管参数对总体失调电压的影响,建立了失调电压的数学模型;采用Chartered 0.18um1P6M工艺对Lewis-Gray型动态比较器进行了电路和版图设计,并利用可快速提取失调电压的定步长仿真方法对其失调电压进行了仿真,结果表明所提出的分析方法可以相对准确的估算失调电压。以该分析方法为基础,本文还提出一种基于总体失调电压影响权重的晶体管分组优化方法,在保证总体面积不变的条件下,可将失调电压有效降低50%以上。经流片测试结果表明,本文所提出的分析和优化方法可应用于高速高精度系统中比较器的设计。     

一种用于AC-DC的可修条振荡器的设计

该文主要设计了一种用于AC-DC电源管理芯片中的频率为100khz的可修条高精度振荡器,它以比较器为核心电路,并利用系统内部产生的恒流源对电容进行充放电,经过控制电路的作用后,使输出波形为线性度很好的三角波。通过HSPICE的仿真结果表明,三角波具有较好的线性度,其信号振荡频率随电源电压和温度的波动变化较小,性能良好,...     

Differential current conveyor based current comparator

A New differential current conveyor based current comparator is presented in this paper. Differential current conveyor II (DCCII) is designed, modified, and exploited as a comparator with reduced propagation delay and power consumption. New DCCII decreases propagation delay and increases comparator accuracy considerably. Simulation results using Hspice and 0.18 μm CMOS technology with 1.8V supply voltage confirms a less than 0.63 ns propagation delay at ±1 μA input current. Average power dissipation in ±1 μA input current has a value of 300 μW.     

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.     

基于90nm CMOS工艺的2GS/s 8-bit 折叠插值ADC的设计*

本文基于90nm CMOS工艺设计了一个单通道 2GSPS, 8-bit 折叠插值模数转换器。本设计采用折叠级联结构,通过在折叠电路间增加级间采样保持器的方法增加量化时间。电路中采用了数字前台辅助校正技术以提高信号的线性度。后仿结果表明,在奈奎斯特采样频率,该ADC的微分非线性DNL<±0.3LSB,积分非线性INL<±0.25LSB,有效位数达到7.338比特。包括焊盘在内的整体芯片面积为880×880 μm2。电路在1.2V 电源电压下功耗为210mW.     

基于Proteus压控变色彩灯控制电路设计

文中介绍了一种基于Proteus的压控变色彩灯控制电路的开发过程,电路主要包括直流稳压电源、基准信号产生电路、电压放大比较电路3个部分,并对设计电路利用Proteus软件进行仿真调试,仿真结果显示可以实现变光变色彩灯功能.