无冲突Petri网系统活标识判定的结构化方法

为了有效求解无冲突Petri网系统活标识的判定及配置优化问题,提出无冲突Petri网系统活标识判定的一种结构化方法。该方法首先求取无冲突Petri网的各强连通分支;然后对每一含有元素个数大于2的强连通分支求取其无同步变迁库所索引集合;最终得到无冲突Petri网系统的无前置库所索引集合,基于该库所元素集合即可实现对活标识的快速判定及配置优化。通过例子具体说明了该方法的实现及应用。分析结果表明,所提方法具有多项式时间复杂度,较易于操作和程序化实现。     

无冲突Petri网的结构活性判定研究

结构活性作为Petri网的重要结构性质,在Petri网活性判定领域具有较高的研究价值.从Petri网有向回路对结构活性的影响入手,分析与判定无冲突Petri网的结构活性,讨论库所元素及其后置变迁之间是否存在有向回路对Petri网结构活性的影响,研究该类Petri网结构活性判定方法的相关条件与结论,得到无冲突Petri网...     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

一种支持向量无冲突访问的质数存储器系统设计方案

ＳＩＭＤ体系结构步入低谷的原因之一是还滑有一个很好的存储器无冲突访问算法。从访问模式的覆盖面来，无疑质数模式最理想的。早在七十年代末的ＢＳＰ并行计算机上就采用了质数存储器的，量由于其它一些问题没有解决，因而带来一些弊端，包括采用交叉开关的实现技术，旨央储空间的记存方式，荐储个数与处理器个数不同等。本文采用了新的实现方式，因而不再存在上述三个问题。     

自动导引车系统资源分配问题的建模及求解

针对自动导引车系统中由任务分派及路径规划共同构成的资源分配问题,基于自动化出入库系统建立模型,提出了一种以粒子群优化(PSO)迭代为框架,并加入无冲突路径规划的优化算法,弥补了以往只按顺序分配任务造成的不足。首先通过粒子群的迭代原理寻找最优任务分派方案;然后通过无冲突的路径规划得到资源分配的结果,同时在解的评价机制中加入了时间窗、工作量均衡及路径无冲突等约束条件,保证方案的可行性。通过模拟自动入库系统,与传统的自动导引车系统调度算法进行了对比,实验结果表明,所提算法在总行驶里程上平均节约了10%左右,且任务分配的均衡性更好,系统的整体效率得到了有效的提升。     

Optimistic Byzantine fault tolerance

The primary concern of traditional Byzantine fault tolerance is to ensure strong replica consistency by executing incoming requests sequentially according to a total order. Speculative execution at both clients and server replicas has been proposed as a way of reducing the end-to-end latency. In this article, we introduce optimistic Byzantine fault tolerance. Optimistic Byzantine fault tolerance aims to achieve higher throughput and lower end-to-end latency by using a weaker replica consistency model. Instead of ensuring strong safety as in traditional Byzantine fault tolerance, nonfaulty replicas are brought to a consistent state periodically and on-demand in optimistic Byzantine fault tolerance. Not all applications are suitable for optimistic Byzantine fault tolerance. We identify three types of applications, namely, realtime collaborative editing, event stream processing, and services constructed with conflict-free replicated data types, as good candidates for applying optimistic Byzantine fault tolerance. Furthermore, we provide a design guideline on how to achieve eventual consistency and how to recover from conflicts at different replicas. In optimistic Byzantine fault tolerance, a replica executes a request immediately without first establishing a total order of the message, and Byzantine agreement is used only to establish a common state synchronization point and the set of individual states needed to resolve conflicts. The recovery mechanism ensures both replica consistency and the validity of the system by identifying and removing the operations introduced by faulty clients and server replicas.     

考虑冲突和拥堵的自动导引车调度与路径规划协同优化

针对自动化集装箱码头自动导引车（AGV）调度与无冲突路径规划问题,提出了AGV冲突拥堵解决策略以生成无冲突路径。首先,考虑堆场缓冲支架的容量,运行路径无拥堵、节点无冲突约束,以最大完工时间最小、AGV总行驶时间最短为目标建立两阶段混合整数规划模型;其次,设计改进的自适应遗传算法、基于冲突拥堵解决策略的迪杰斯特拉算法求得AGV调度方案与无冲突路径。算例分析结果表明：改进的自适应遗传算法相较遗传算法平均求解时间降低了13.56%,且目标函数平均差距率为9.01%;基于冲突拥堵解决策略相较停车等待策略使得水平运输区拥堵度降低67.6%,AGV等待时间减少66.7%。可见,所提算法求解质量高且速度快,同时验证了所提策略的有效性。     

混合基可重构FFT处理器的设计与实现

本文提出了一种新型混合基可重构FFT处理器,由支持基-2/3FFT的新型可重构蝶形单元和多路并行无冲突的存储器组成,实现了FFT过程中多路数据并行性和操作的连续性.本设计在TSMC28nm工艺下的最高频率为1.06GHz,同时在Xilinx的XC7V2000T FPGA芯片上搭建了混合基FFT处理器硬件测试系统.对混合基FFT处理器的FPGA硬件测试结果表明,本设计支持基-2、基-3和基-2/3混合模式FFT变换,且执行速度达到给定蝶乘器数量下的理论周期值,对单精度浮点数,混合基FFT处理器可提供10-5的结果精度.     

Efficient Algorithms for Slot-Scheduling and Cycle-Scheduling of Video Streams on Clustered Video Servers

The granularity of scheduling video streams can be categorized as cycle-scheduling and slot-scheduling where a time cycle is further divided into time slots. To avoid resource conflict and thereby increase throughput of clustered video servers, slot-scheduling using conflict-free scheduling and especially cycle-scheduling using full-duplex scheduling and ordered scheduling are presented in the paper. Also, the analysis of the pros and cons of applying slot-scheduling and cycle-scheduling on clustered video servers are discussed.