Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration

General-purpose processors are often incapable of achieving the challenging cost, performance, and power demands of high-performance applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a processor for a particular application. The processor is extended with hardware in the form of a set of custom function units and instruction set extensions. To effectively identify opportunities for creating custom hardware, a dataflow graph design space exploration engine heuristically identifies candidate computation subgraphs without artificially constraining their size or shape. The engine combines estimates of performance gain, cost, and inherent limitations of the processor to grow candidate graphs in profitable directions while pruning unprofitable paths. This paper describes the dataflow graph exploration engine and evaluates its effectiveness across a set of embedded applications.     

The Visualization Input Pipeline - Enabling Semantic Interaction in Scientific Visualization

Scientific Visualization systems are primarily output-oriented, Users can specify and change parameters that are controlling the visualization process, which will result in different data representations or images respectively. But no mechanism is provided to really interact with the application data (semantic interaction) that has been changed step by step by the process of visualization. In this paper general concepts are elaborated and presented to achieve semantic interaction in dataflow environments for Scientific Visualization.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

Memory-constrained Block Processing for DSP Software Optimization

Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded software for DSP systems. Task-level vectorization, or block processing, is a useful dataflow graph transformation that can significantly improve execution performance by allowing subsequences of data items to be processed through individual task invocations. In this way, several benefits can be obtained, including reduced context switch overhead, increased memory locality, improved utilization of processor pipelines, and use of more efficient DSP oriented addressing modes. On the other hand, block processing generally results in increased memory requirements since it effectively increases the sizes of the input and output values associated with processing tasks. In this paper, we investigate the memory-performance trade-off associated with block processing. We develop novel block processing algorithms that carefully take into account memory constraints to achieve efficient block processing configurations within given memory space limitations. Our experimental results indicate that these methods derive optimal memory-constrained block processing solutions most of the time. We demonstrate the advantages of our block processing techniques on practical kernel functions and applications in the DSP domain.

Fractional Rate Dataflow Model for Efficient Code Synthesis

Automatic code synthesis from dataflow program graphs is a promising high-level design methodology for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has been an active research subject to reduce the gap in terms of memory requirements between the synthesized code and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia applications. Extended SDF model with fractional rate has been implemented in our system design environment called PeaCE(Ptolemy extension as Codesign Environment).     

面向NGB的集中式WLAN无线城市业务数据流向设计

通过建设WLAN无线网络可以使广电运营商的三网融合业务具备移动互联网化基础。本文提出应在NGB网络之上承载WLAN无线网络,并设计出一种发挥NGB网络特性、保障NGB已有业务不受干扰、可大规模快速部署的集中式WLAN业务数据流向方案。     

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations.We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the trade-offs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.     

Reliability models for computer systems: An overview including dataflow graphs

The reliability of a system is the probability that the system will perform its intended mission under given conditions. This paper provides an overview of the approaches to reliability modelling and identifies their strengths and weaknesses. The models discussed include structure models, simple stochastic models and decomposable stochastic models. Ignoring time-dependence, structure models give reliability as a function of the topological structure of the system. Simple stochastic models make direct use of the properties of underlying stochastic processes, while decomposable models consider more complex systems and analyse them through subsystems. Petri nets and dataflow graphs facilitate the analysis of complex systems by providing a convenient framework for reliability analysis.     

面向多领域的可视化应用开发平台MOVADP

ＭＯＶＡＤＰ是一个面向多领域的可视化应用开发平台，文中主要介绍了该平台的软件结构和实现技术，ＭＯＶＡＤＰ以数据流机制为核心，采用可视编程技术，为用户开发可视化应用提供了一个文凭交互的模块级图形编程环境，与同类平台相比，ＭＯＶＡＤＰ的特点在于，引入了ＩＦＴＨＥＮ－ＥＬＳＥ，ＷＨＩＬＥ－ＬＯＯＰ等控制结构，支持用户构建复杂的可化应用流图；支持“ｌａｚｙｅｖａｌｕａｔｉｏｎ”命令驱动方式下的流图局部运行     

静态检测中断驱动程序的数据竞争

直接运行于微控制器上的中断驱动程序中可能存在一种重要的程序错误:数据竞争.然而当前主流的数据竞争静态检测技术因其服务于多线程模型程序而不适用.设计简明、易用的中断特征描述语言可以使得竞争检测具有平台无关性;同时,提出了一个流敏感的、上下文敏感的、考虑中断驱动程序原子性、易变性和部分随机性的数据竞争检测算法.该算法具有高效、精确的特点.实验表明,其检测时间与代码规模基本呈线性关系,分析17850行代码仅用时3.6s;同时,相比于基于锁集技术的典型数据竞争检测方法,其准确率平均是后者的2.13倍.