Methods of Verifying Continuous Automatic Belt Weighers: State and Prospects

The basic methods of verifying continuous automatic belt weighers are described. A comparative analysis of these methods on the basis of experimental studies is made and ways of implementing the results in industry are recommended.     

A survey of parallel execution strategies for transitive closure and logic programs

An important feature of database technology of the nineties is the use of parallelism for speeding up the execution of complex queries. This technology is being tested in several experimental database architectures and a few commercial systems for conventional select-project-join queries. In particular, hash-based fragmentation is used to distribute data to disks under the control of different processors in order to perform selections and joins in parallel. With the development of new query languages, and in particular with the definition of transitive closure queries and of more general logic programming queries, the new dimension of recursion has been added to query processing. Recursive queries are complex; at the same time, their regular structure is particularly suited for parallel execution, and parallelism may give a high efficiency gain. We survey the approaches to parallel execution of recursive queries that have been presented in the recent literature. We observe that research on parallel execution of recursive queries is separated into two distinct subareas, one focused on the transitive closure of Relational Algebra expressions, the other one focused on optimization of more general Datalog queries. Though the subareas seem radically different because of the approach and formalism used, they have many common features. This is not surprising, because most typical Datalog queries can be solved by means of the transitive closure of simple algebraic expressions. We first analyze the relationship between the transitive closure of expressions in Relational Algebra and Datalog programs. We then review sequential methods for evaluating transitive closure, distinguishing iterative and direct methods. We address the parallelization of these methods, by discussing various forms of parallelization. Data fragmentation plays an important role in obtaining parallel execution; we describe hash-based and semantic fragmentation. Finally, we consider Datalog queries, and present general methods for parallel rule execution; we recognize the similarities between these methods and the methods reviewed previously, when the former are applied to linear Datalog queries. We also provide a quantitative analysis that shows the impact of the initial data distribution on the performance of methods. Recommended by: Patrick Valduriez     

分置式牛津型斯特林制冷机的数值分析与实验验证

对分置式牛津型斯特林制冷机进行了数值计算 ,介绍了计算模型考虑到的众多不可逆因素。通过对计算结果与实验结果的对比 ,验证了本文数值计算的准确性 ,说明本文计算模型与数值处理方法是切实可行的     

Putting it all together – Formal verification of the VAMP

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.     

二厘米微波衰减标准装置不确定度的验证

采用传递比较法对二厘米微波衰减标准装置不确定度进行了验证。测量标准装置的重复性以组内实验标准偏差sn(A)定量表征，测量标准装置的稳定性用组间实验标准偏差sm定量表征。     

基于非锐化掩模的实时自适应图像增强算法

针对传统的非锐化掩模算法的局限性,依据图像中各像素点及以其为中心的若干相邻像素点的均方差值,提出了自适应图像增强算法的原理,并分析其硬件实现方法,然后给出了该算法与其它算法应用于图像增强的对比结果,最后在FPGA（field programmable gate array）实验板上进行验证.实验结果表明,此算法有效的增强图像的细节区域,防止图像边缘区域出现过冲现象,抑制图像平坦区域的噪声放大.因此,该算法取得了良好的视觉效果,硬件实现简单,适合于实时条件下图像的增强.     

Delamination Analysis for Laminated Composites. II: Numerical Verification

A validation of the delamination analysis models developed in a companion paper is provided through comparisons of predictions with finite‐element and elasticity solutions. The models are applied to the analysis of composite compression specimens reinforced with end tabs. An elasticity solution for the gage section of the specimens is developed. A comparison of the characteristic roots shows that the predictions of the models include the material and geometric parameters that control the behavior, and the roots corresponding to the basic stretching and bending modes are accurately predicted. The stress distribution at the interface between tabs and specimen is in good agreement with a finite‐element simulation. The interlaminar shear and peel stresses show an exponential increase with a maximum intensity at the free edges of the tabs. The behavior of previously tested specimens is explained; and practical guidelines for specimen design are provided to avoid unwanted extraneous modes of failure. The influence of the deformation modes associated with each model is investigated. An assessment of the accuracy and level of complexity is presented.     

用边界元法提取VLSI版图电阻

介绍了ＶＬＳＩ版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。该算法采用变节点单元，较好地解决了实际问题中经常出现的角点问题。通过应用该算法对几个实例进行提取，证明使用本文的算法不仅在精度上而且在占用ＣＰＵ时间上都取得了令人满意的效果     

A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol

We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level). We use the model to show that an 18-bit/cell biphase mark protocol reliably sends messages of arbitrary length between two processors provided the ratio of the clock rates is within 5% of unity.