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1.
Compilation Techniques for Multimedia Processors   总被引:5,自引:0,他引:5  
The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.  相似文献
2.
基于Trimedia DSP的H.264解码算法优化   总被引:2,自引:0,他引:2  
H.264是最新的视频编码标准,具有非常优良的编码性能,但它的算法复杂度也很高,很难满足实时应用的需要。论文详细分析了影响H.264解码速度的因素,提出了基于TrimediaDSP平台的优化方案。该方案通过缩减不必要的判断、避免频繁的内存访问、优化内存的分配与使用、合理使用循环展开以及采用DSP专用指令等方法来提高H.264解码算法的运算速度。测试结果表明:优化后的代码运行速度平均提高了8倍,在主频为200MHz的TrimediaDSP上能实时解码CIF格式的H.264基本码流。  相似文献
3.
3种提高软件流水有效性的算法:比较和结合   总被引:1,自引:0,他引:1       下载免费PDF全文
李文龙  陈彧  林海波  汤志忠 《软件学报》2005,16(10):1822-1832
软件流水是开发循环程序指令级并行性的技术,它通过并行执行连续的多个循环体来加快循环的执行速度.在软件流水中,循环体的重叠增加了寄存器需求,导致寄存器压力增大,当目标处理机所提供的寄存器不足时,软件流水可能失败.在Itanium处理机上评估了NAS和SPEC2000基准程序中的软件流水循环的寄存器需求,发现静态寄存器不足是造成软件流水失败的主要原因,提出了3种增加软件流水个数、提高软件流水有效性的算法:限制循环展开因子的算法(register sensitive unrolling,简称RSU)、堆栈寄存器分配算法(stacked registerallocation,简称SRA)以及变量类型转换的算法(variabletype conversion,简称VTC).RSU根据静态寄存器需求确定一个合理的展开因子,增加了软件流水的成功率;SRA和VTC分别使用空闲的堆栈寄存器和旋转寄存器来充当静态寄存器,提高了寄存器的利用率.在面向Itanium处理器的开放源码编译器ORC(open research compiler)上实现了这3种算法,通过NAS程序的测试比较了这3种算法的有效性,同时对它们的结合应用进行了研究和实验.  相似文献
4.
基于四阶段人工优化的软件流水技术   总被引:1,自引:1,他引:0       下载免费PDF全文
代码体积是优化存储资源有限的嵌入式系统的重要因素之一。针对该特点,使用oprofile性能分析工具,以EEMBC基准程序集作为工作负载,提出四阶段人工优化软件流水方法(FPMO)。电信类的自相关程序实验结果表明,FPMO以2.04%的代码增量为代价换来40.678%的性能提升,而单纯的编译器自动优化则以33.35%的体积膨胀换来38.33%的性能提升。  相似文献
5.
分段约束的超字并行向量发掘路径优化算法   总被引:1,自引:0,他引:1  
超字并行(SLP)是一种针对基本块的向量并行发掘方法,结合循环展开可以发掘更多的并行性,但同时也会产生过多的发掘路径.针对上述问题,提出了一种分段约束的SLP发掘路径优化算法;采用分段的冗余删除方法,来保证冗余删除后段的同构性.采用段间的SLP发掘,来约束发掘路径;最后进行pack调整来处理访存重叠的情况.实验结果表明,该方法有效增强了SLP向量化功能,对于测试程序,向量化的平均加速比接近2.  相似文献
6.
利用循环分割和循环展开避免Cache代价   总被引:1,自引:0,他引:1       下载免费PDF全文
刘 利  陈 彧  乔 林  汤志忠 《软件学报》2008,19(9):2228-2242
存储系统与处理器之间的速度差距逐渐变大,为此,cache使用了分级机制,但这也带来了额外的存储延迟(cache代价).提出一种利用循环分割和循环展开相结合避免cache代价的PCPLPU(prevent cache penalty by loop partition-unrolling)算法.实验结果表明,PCPLPU算法能够有效避免循环代价,提高程序性能.  相似文献
7.
Loop unrolling is a well known loop transformation that has been used in optimizing compilers for over three decades. In this paper, we address the problems of automatically selecting unroll factors for perfectly nested loops, and generating compact code for the selected unroll factors. Compared to past work, the contributions of our work include (i) a more detailed cost model that includes register locality, instruction-level parallelism and instruction-cache considerations; (ii) a new code generation algorithm that generates more compact code than the unroll-and-jam transformation; and (iii) a new algorithm for efficiently enumerating feasible unroll vectors. Our experimental results confirm the wide applicability of our approach by showing a 2.2× speedup on matrix multiply, and an average 1.08× speedup on seven of the SPEC95fp benchmarks (with a 1.2× speedup for two benchmarks). Larger performance improvements can be expected on processors that have larger numbers of registers and larger degrees of instruction-level parallelism than the processor used for our measurements (PowerPC 604).  相似文献
8.
The performance of modern microprocessors is greatly affected by cache behavior, instruction scheduling, register allocation and loop overhead. High-level loop transformations such as fission, fusion, tiling, interchanging and outer loop unrolling (e.g., unroll and jam) are well known to be capable of improving all these aspects of performance. Difficulties arise because these machine characteristics and these optimizations are highly interdependent. Interchanging two loops might, for example, improve cache behavior but make it impossible to allocate registers in the inner loop. Similarly, unrolling or interchanging a loop might individually hurt performance but doing both simultaneously might help performance. Little work has been published on how to combine these transformations into an efficient and effective compiler algorithm. In this paper, we present a model that estimates total machine cycle time taking into account cache misses, software pipelining, register pressure and loop overhead. We then develop an algorithm to intelligently search through the various, possible transformations, using our machine model to select the set of transformations leading to the best overall performance. We have implemented this algorithm as part of the MIPSPro commercial compiler system. We give experimental results showing that our approach is both effective and efficient in optimizing numerical programs.  相似文献
9.
提出了一种在高性能RISC芯片上进行图象中低层处理的寄存器优化方法,使用该方法能够处理速度提高将近一倍,在TMS320c40上所做的实验表明应用该方法能取得较好的效果。  相似文献
10.
本文提出一种面向嵌入式低功耗的基于执行频率的循环展开优化方法,根据循环的执行频率,积极展开一些频繁被执行的循环,不展开那些很少被执行的循环。所有这些都在GCC4.0.0上进行了实现,并在sim-panalyzer功耗模拟器上对12个Benchmarks进行了测试,结果表明,相对于传统的循环展开优化,新的优化方法可以有效的降低功耗,并且减少了代码量的增加。  相似文献
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