An electrical circuit analogy model for analyses and optimizations of the Stirling-type pulse tube cryocooler

The existing electrical circuit analogy (ECA) models are mainly used to optimize the inertance tube and to analyze the crude phase of the dynamic pressure and the volume flow rate. The specific analyses and optimizations of other components or the whole Stirling-type pulse tube cryocooler (SPTC) with the ECA model have not been carried out. In this paper, a new ECA model including the main components of the SPTC such as regenerator, pulse tube, phase shifter and reservoir has been developed. To improve the practicability of the ECA model, based on the basic governing equations, calculation expressions of the above components are worked out, and their equivalent analogical electrical elements are defined according to the analogy theory. Through the developed ECA model, the specific pressure and volume flow rate at any position can be acquired. Further optimizations on the SPTC based on the ECA model show that, with the same pressure and PV power at the warm end of the regenerator, there exists an optimal phase angle between the pressure and the volume flow rate for the SPTC to achieve the highest gross cooling capacity. In addition, with the same ratio of the pressure to the volume flow rate and the same phase angle between them at the warm end of the regenerator, when the regenerator ineffectiveness loss is neglected, the SPTC efficiency keeps constant with variations of the PV power, however, the efficiency will increase with the increase of the PV power if the loss is considered.     

Applying a hybrid job shop procedure to a Belgian manufacturing company producing industrial wheels and castors in rubber

In this paper, several methods for job shop scheduling are combined, adjusted and successfully applied to a real-world scheduling problem at a Belgian manufacturer producing industrial wheels and castors in rubber. The procedure is an extension of a hybrid shifting bottleneck procedure with a tabu search algorithm while incorporating various company specific constraints. The various extensions to cope with the company specific constraints have a strong similarity with the complex job shop problem formulation of Mason, Fowler, and Carlyle (2002). The new procedure is used as a simulation engine to test the relevance of various scenarios in order to improve the current planning approach of the company. A detailed computational experiment highlights the main contribution of the novel procedure for the company.     

Analysis of the behaviour of a yield-control support system in squeezing rock

Recent innovations in yield-control support systems allow to increase the rate of advance when tunnelling in difficult conditions is associated with severely squeezing rock. Such systems which imply the insertion in the lining of highly deformable concrete elements are being adopted successfully in tunnelling projects using conventional excavation methods. The Saint Martin access adit excavated in a Carboniferous Formation along the Base Tunnel of the Lyon-Turin rail line is presented as a case study. Numerical analyses are discussed to compare the results of computed and measured performance of a typical monitored section and to find out possible optimizations of the support system adopted.     

I386到Alpha动态二进制翻译中的代码缓存管理优化

动态二进制翻译是跨平台软件移植的最重要手段之一,如何对其进行优化,提高翻译效率一直是研究的热点。文章对I386到Alpha平台的动态二进制翻译进行了研究,提出了一种较好的翻译缓存管理策略,在FIFO的基础上将翻译缓存划分为两级进行管理。以QEMU动态二进制翻译器为实验平台进行测试,结果表明,采用此方法可以提升翻译速度约3%。     

I386到Alpha动态二进制翻译中的代码缓存管理优化

动态二进制翻译是跨平台软件移植的最重要手段之一,如何对其进行优化,提高翻译效率一直是研究的热点。文章对I386到Alpha平台的动态二进制翻译进行了研究,提出了一种较好的翻译缓存管理策略,在FIFO的基础上将翻译缓存划分为两级进行管理。以QEMU动态二进制翻译器为实验平台进行测试,结果表明,采用此方法可以提升翻译速度约3%。     

Vector data flow analysis for SIMD optimizations on OpenCL programs

Multi‐core systems equipped with micro processing units and accelerators such as digital signal processors (DSPs) and graphics processing units (GPUs) have become a major trend in processor design in recent years in attempts to meet ever‐increasing application performance requirements. Open Computing Language (OpenCL) is one of the programming languages that include new extensions proposed to exploit the computing power of these kinds of processors. Among the newly extended language features, the single‐instruction multiple‐data (SIMD) linguistics and vector types are added to OpenCL to exploit hardware features of the accelerators. The addition makes it necessary to consider how traditional compiler data flow analysis can be adopted to meet the optimization requirements of vector linguistics. In this paper, we propose a calculus framework to support the data flow analysis of vector constructs for OpenCL programs that compilers can use to perform SIMD optimizations. We model OpenCL vector operations as data access functions in the style of mathematical functions. We then show that the data flow analysis for OpenCL vector linguistics can be performed based on the data access functions. Based on the information gathered from data flow analysis, we illustrate a set of SIMD optimizations on OpenCL programs. The experimental results incorporating our calculus and our proposed compiler optimizations show that the proposed SIMD optimizations can provide average performance improvements of 22% on x86 CPUs and 4% on advanced micro devices GPUs. For the selected 15 benchmarks, 11 of them are improved on x86 CPUs, and six of them are improved on advanced micro devices GPUs. The proposed framework has the potential to be used to construct other SIMD optimizations on OpenCL programs. Copyright © 2015 John Wiley & Sons, Ltd.     

Link adaptation for wireless systems

To improve the robustness and reliability of wireless transmissions, two complementary link adaptation techniques are employed: adaptive modulation and coding (AMC) at the physical layer and hybrid automatic retransmission request (HARQ) at the medium access control layer. Because of their effectiveness in combating errors induced by the wireless channel, AMC and HARQ are now integral components of most emerging broadband wireless system standards, for example, LTE and WiMAX. Spectral efficiency (SE) as measured in bit per second per Hertz is one important parameter used to characterize a wireless system for comparison between different systems or between different configurations of the same system. This work provides a holistic approach of cross‐layer optimizations with the intent of maximizing SE by combining AMC and HARQ. It formulates closed‐form equations for calculating the average SE for wireless systems with the Rayleigh fading channel model. A new online algorithm is developed to optimize SE for both Rayleigh and non‐Rayleigh fading channel. Simulations using proven LTE model are performed to compare SE obtained from closed‐form equations and the developed algorithm for different system configurations. With the developed algorithm to determine how many retransmissions required in addition to the initial transmission in advance depending on the current wireless channel condition, the latency can be reduced up to 24 ms when sending the initial transmission and all of its retransmissions sooner than waiting for retransmission requests as is done previously. Copyright © 2012 John Wiley & Sons, Ltd.     

卧式管内流体动力自动清洗螺旋纽带的结构关系研究

本文提出了卧式冷凝管内流体动力自动清洗螺旋纽带结构优化目标。对管内插有自转式螺旋纽带的流体进行了运动分析，进而采用理论与试验测量相结合的办法，建立了插有自转式螺旋纽带的管中流体所受的清洗扭矩、流体阻力系数及对流体传热努塞尔准数与纽带结构参数的理论计算式，论述了电厂真空冷凝器污垢自动清洗纽带的结构优化研究的结果。     

Improving WCET by applying worst-case path optimizations

It is advantageous to perform compiler optimizations that attempt to lower the worst-case execution time (WCET) of an embedded application since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been considerable effort to develop compiler optimizations to improve these paths in order to reduce the average-case execution time (ACET). In this paper, we describe an approach to reduce the WCET by adapting and applying optimizations designed for frequent paths to the worst-case (WC) paths in an application. Instead of profiling to find the frequent paths, our WCET path optimization uses feedback from a timing analyzer to detect the WC paths in a function. Since these path-based optimizations may increase code size, the subsequent effects on the WCET due to these optimizations are measured to ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate these WC path optimizations and present results showing the decrease in WCET versus the increase in code size. A preliminary version of this paper entitled “Improving WCET by optimizing worst-case paths” appeared in the 2005 Real-Time and Embedded Technology and Applications Symposium. Wankang Zhao received his PhD in Computer Science from Florida State University in 2005. He was an associate professor in Nanjin University of Post and Telecommunications. He is currently working for Datamaxx Corporation. William Kreahling received his PhD in Computer Science from Florida State University in 2005. He is currently an assistant professor in the Math and Computer Science department at Western Carolina University. His research interests include compilers, computer architecture and parallel computing. David Whalley received his PhD in CS from the University of Virginia in 1990. He is currently the E.P. Miles professor and chair of the Computer Science department at Florida State University. His research interests include low-level compiler optimizations, tools for supporting the development and maintenance of compilers, program performance evaluation tools, predicting execution time, computer architecture, and embedded systems. Some of the techniques that he developed for new compiler optimizations and diagnostic tools are currently being applied in industrial and academic compilers. His research is currently supported by the National Science Foundation. More information about his background and research can be found on his home page, http://www.cs.fsu.edu/∼whalley. Dr. Whalley is a member of the IEEE Computer Society and the Association for Computing Machinery. Chris Healy earned a PhD in computer science from Florida State University in 1999, and is currently an associate professor of computer science at Furman University. His research interests include static and parametric timing analysis, real-time and embedded systems, compilers and computer architecture. He is committed to research experiences for undergraduate students, and his work has been supported by funding from the National Science Foundation. He is a member of ACM and the IEEE Computer Society. Frank Mueller is an Associate Professor in Computer Science and a member of the Centers for Embedded Systems Research (CESR) and High Performance Simulations (CHiPS) at North Carolina State University. Previously, he held positions at Lawrence Livermore National Laboratory and Humboldt University Berlin, Germany. He received his Ph.D. from Florida State University in 1994. He has published papers in the areas of embedded and real-time systems, compilers and parallel and distributed systems. He is a founding member of the ACM SIGBED board and the steering committee chair of the ACM SIGPLAN LCTES conference. He is a member of the ACM, ACM SIGPLAN, ACM SIGBED and the IEEE Computer Society. He is a recipient of an NSF Career Award.     

Understanding the behavior of compiler optimizations

Compiler optimizations are difficult to implement and add complexity to a compiler. For this reason, compiler writers are selective about implementing them: they implement only the ones that they believe will be beneficial. To support compiler writers in this, we describe a method for measuring the cost and benefits of compiler optimizations, both individually and in synergy with other optimizations. We demonstrate our method by presenting results for the optimizations implemented in the Jikes Research Virtual Machine on the PowerPC and IA32 platforms. Copyright © 2006 John Wiley & Sons, Ltd.