基于三维胞元空间的MA双向并行路由算法

针对传统移动代理(MA)在监测无线传感器网络(WSNs)的感兴趣信息时产生的延迟较大和能耗较多问题,提出了基于三维胞元空间的MA双向并行(3D-BPMA)路由算法.3D-BPMA将MA与传统的客户/服务器(c/S)模式相结合,在胞元内利用C/S模式搜集信息,在单层胞元系统和路由器与路由器之间采用MA双向并行的策略进行传输.仿真结果表明:3D-BPMA与LCF,DSG-MIP算法相比减少了平均响应时间和网络平均能耗,提高了MA发送率.     

Mixed coordination mechanisms for scheduling games on hierarchical machines

In this paper, we study scheduling games under mixed coordination mechanisms on hierarchical machines. The two scheduling policies involved are ‐ and ‐, where ‐ (resp., ‐) policy sequences jobs in nondecreasing order of their hierarchies, and jobs of the same hierarchy in nonincreasing (resp., nondecreasing) order of their processing times. We first show the existence of a Nash equilibrium. Then we present the price of anarchy and the price of stability for the games with social costs of minimizing the makespan and maximizing the minimum machine load. All the bounds given in this paper are tight.     

离心泵并联运行工况点的数值求解

建立了求解多台不同型号离心泵并联运行工况点的数学模型,给出了用数值计算中的“二分法”求解该模型的方法,并附有用Exce l计算的实例。     

SIMPLIS环境中开关电源集成电路控制器模型的开发及应用

介绍现代开关电源行业仿真工作的意义和现状,以及专用仿真软件包SIM etrix/SIMPLIS的优点和不足。通过实例给出SIMPLIS环境中集成电路控制芯片的建模过程,并就其中的关键技术予以简单讨论。     

串行及并行A/D转换器在高速数据采集中的采样差别性分析

串行和并行接口模式是A/D转换器诸多分类中的一种,但却是应用中器件选择的一个重要指标.在同样的转换分辨率及转换速度的前提下,不同的接口方式不但影响了电路结构,更重要的是将在高速数据采集的过程中对采样周期产生较大影响.本文通过12位串行ADC ADS7822和并行ADC ADS774与AT89C51的接口电路,给出二者采样时间的差异性.     

浅谈计算软件的开发

软件开发重要的是 :确定编程语言 ,代码设计 ,程序设计 ,软件试验 ,人员培训等步骤     

Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.