Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register (LFSR) are suitable for constrained environments, such as satellite communications, radio frequency identification devices tag, sensor networks and Internet of Things, due to its simple hardware structures, high speed encryption and lower power consumption. LFSR, as a cryptographic primitive, has been used to generate a maximum period sequence. Because the switching of the status bits is regular, the power consumption of the LFSR is correlated in a linear way. As a result, the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks. In this paper, a new design of LFSR against power attacks is proposed. The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop. The design method has been implemented easily by circuits in this new design in comparison with the others.     

高性能通用DSP寄存器扩展设计实现方法

本文提出一种高性能通用DSP扩展寄存器的设计及实现方法,该方法是我国自主研发的高性能通用DSP中实现寄存器堆扩展的一种新方法,其优点是在不影响现有指令集及指令机器码位宽的前提下,实现对处理器内部寄存器堆的成比例扩展。通过在我国自主研制DSP上的实际应用,证明了该扩展方法的有效性和实用性。     

专用薄板卷筒成型机数控系统的设计

该系统是一个分布式的全自动专用数控系统，用来加工汽车的消音器．采用工业PC为主控系统，利用PLC控制薄板卷筒系统，通过RS-485接口与主控PC进行通讯．采用WINCC工控软件平台，研制了系统软件，产品数据管理软件．专用数控系统大大提高了专业生产企业的自动化水平．     

基于SystemView的4位m序列发生器数学模型的分析及电路设计

通过对m序列的数学模型研究分析,运用System View软件进行了4级移位寄存器模型的仿真,并对4位m序列生成器电路进行了设计研究,探讨了实现m序列的生成过程。仿真表明所设计的电路合理,其结果与理论分析一致。     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

Novel way to research nonlinear feedback shift register

In this paper,we regard the nonlinear feedback shift register（NLFSR） as a special Boolean network,and use semi-tensor product of matrices and matrix expression of logic to convert the dynamic equations of NLFSR into an equivalent algebraic equation. Based on them,we propose some novel and generalized techniques to study NLFSR. First,a general method is presented to solve an open problem of how to obtain the properties（the number of fixed points and the cycles with different lengths） of the state sequences produced by a given NLFSR,i.e.,the analysis of a given NLFSR. We then show how to construct all 2^2^n-（l-n）/2^2^n-lshortest n-stage feedback shift registers（nFSR） and at least 2^2^n-（l-n）-1/2^2^n-l-1shortest n-stage nonlinear feedback shift registers（nNLFSR） which can output a given nonperiodic/periodic sequence with length l. Besides,we propose two novel cycles joining algorithms for the construction of full-length nNLFSR. Finally,two algorithms are presented to construct 2^2^n-2-1different full-length nNLFSRs,respectively.     

CMOS APS用移位寄存器抗SEU加固方法

电离辐射环境中使用的CMOS 有源像素图像传感器(APS)的基于反相器的准静态移位寄存器容易发生单粒子翻转(SEU)，而致使CMOS APS不能正常工作。本文对基于反相器的准静态移位寄存器中的单粒子翻转效应进行了分析，其对单粒子瞬态(SET)最敏感的节点存在于反相器的输入端，反相器的输入阈值电压和输入节点电容决定了其抗SEU的能力。提出了用施密特触发器代替反相器的加固方案，因施密特触发器的电压传输特性存在一滞回区间，所以有更高的翻转阈值，从而可获得更好的抗SEU能力。仿真结果表明，采用施密特触发器的移位寄存器结构较原电路结构的抗SEU能力提高了约10倍。     

INFORMATION THEORETIC APPROACH TO SECURE LSFR CIPHERS

To break a normal LFSR cipher, a cryptanalyst needs only 2n bits of corresponding plain and ciphertext, where n is the number of stages of the shift register.[l] In this paper, a method of substituting completely random characters into the ciphertext and therefore preventing the encipherment of a full 2n-length sequence (under its proper key) will be discussed. Due to the high redundancy of English, a cipher containing several completely random characters will still be readable.     

基于FPGA密集假目标干扰的实现

在现代电子战中,应对新体制雷达、雷达干扰机转向采用欺骗性干扰方式,结合DRFM的机理,介绍了可控变间隔的密集假目标产生机理,基于FPGA内部IP核 FIFO 产生密集假目标,通过控制FIFO的存储深度来实现假目标的延迟时间;通过开关控制假目标的输出数量。仿真分析了假目标产生机理的正确性,同时验证了密集假目标产生的硬件可实现性,并给出了硬件实现假目标调幅调频的方法,为相关雷达干扰机硬件实现提供了参考。