CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.     

SoC测试访问机制和测试壳的蚁群联合优化

针对系统级芯片(SoC)测试壳优化和测试访问机制的测试总线划分问题,提出了基于蚁群算法的SoC Wrapper/TAM联合优化方法.构造蚁群算法时首先进行IP核的测试壳优化,用于缩短最长扫描链长度,减少单个IP核的测试时间;在此基础上进行TAM结构的蚁群优化,通过算法迭代逼近测试总线的最优划分,从而缩短SoC测试时间.对ITC2002基准SoC电路进行实验的结果表明,该方法能有效地解决SoC测试优化问题.     

FPGA的动力电池检测系统研究

为提高动力电池使用效率,提出了一种基于FPGA的动力电池检测系统的设计方案.采用AD转换芯片实现对电池电压、电流的采集,数字温度传感器对温度进行采集,再通过软件实现对数据的处理和实时显示.系统运行稳定,数据处理能力强,集成度高,易于扩展.     

SCV及其在SoC验证中的应用

片上系统(System on Chip,SoC)是集成电路设计发展的趋势,验证在整个SoC设计中工作量巨大且至关重要.应用验证领域的最新成果SCV(SystemCVerification),提出了通过设计用户定义的事务接口(Transactor),对RTL(RegisterTransferLevel)级设计进行事务级验证的策略,并对一个具体的FIFO事例进行了验证.     

多轴伺服控制器的片上系统设计

针对数字伺服控制算法及片上系统集成技术的问题,依据矢量控制和伺服系统设计理论,建立了磁场定向矢量控制器、速度控制器和位置控制器等高性能IP核模型,开发了坐标变换、速度测量、SVPWM、反时限保护、PID调节器、电子齿轮、前馈控制及滤波器等关键算法模块,详细规划了各模块的调度时序。在此基础上,进一步集成了RISC微处理器模块,并采用时分复用设计方法,在FPGA工艺平台中最终实现了多轴伺服控制器片上系统。实验结果表明,该芯片能够接收脉冲命令、模拟命令或数字命令,既可以工作在位置控制模式,也可以配置为速度伺服或力矩驱动模式,每个轴的运行是相对独立的,并且控制参数在线可编程。     

一种基于元操作的宏模块功耗建模方法

为了有效支持系统芯片(SOC)的功耗分析和第三方IP的功耗评估,并有效保护知识产权,提出了元操作的概念,给出了一种基于元操作的宏模块功耗建模方法,建立了元操作功耗模型.该模型是一种周期精确的功耗模型,它描述了宏模块每个时钟周期的动态功耗变化情况.文中论述了这一模型的开发方法和使用方法,并指出,建立元操作功耗模型的关键是模块的功能定义、模块的功能到元操作的映射以及门级功耗样本的产生和收集.通过与门级功耗分析的实验数据对比,此元操作功耗模型的功耗分析误差在4%以内,功耗分析效率可以提高百倍以上.     

过程级动态划分的RSoC软硬件双通信模式

软硬件通信模式的选择对软硬件通信效率产生很大影响.根据硬件函数的特点,提出一种根据软硬件通信量自适应地选择通信模式的软硬件双通信模式,并构建了一种通信模式自适应决策算法,软硬件通信模式的选择对用户透明.实验表明,根据运行时系统状态自适应地选择通信模式,软硬件通信效率得到优化,面积开销也适当减少.     

片上网络拓朴优化:在离散平面上布局与布线

微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.