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排序方式: 共有140条查询结果,搜索用时 46 毫秒
1.
高速网络下的分布式实时入侵检测系统   总被引:18,自引:0,他引:18  
随着网络技术的飞速发展,网络安全问题日益突出。网络入侵检测系统需要处理大量的数据,处理能力的缺乏会引起入侵事件的漏报,提高入侵检测系统的处理能力是目前急需解决的关键问题。DRTIDS(distributed real-time intrusion detection system for high-speed networks)是一个由单个分析节点和多个探测节点组成的、工作在高速网络下的分布式网络入侵检测系统。DRTIDS的分析节点执行基于网络主机的流量分配策略,保证尽可能地平衡分配网络流量,从而尽可能地发挥整个系统的处理能力。  相似文献
2.
Retiming synchronous circuitry   总被引:9,自引:0,他引:9  
This paper describes a circuit transformation calledretiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex setV is a collection of combinational logic elements and the edge setE is the set of interconnections, each of which may pass through zero or more registers. We give anOVE¦lg¦V¦) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a chacterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.This research was supported in part by the Defense Advanced Research Projects Agency under Contract N00014-80-C-0622 and by the Office of Naval Research under Contract N00014-76-C-0370. Charles Leiserson was supported in part by an NSF Presidential Young Investigator Award with matching funds provided by AT&T Corporation, IBM Corporation, and Xerox Corporation. Most of the results reported here were obtained while James Saxe was in the Computer Science Department at Carnegie-Mellon University. During part of that period, he was supported by an IBM graduate fellowship.  相似文献
3.
An Analytical Delay Model   总被引:5,自引:0,他引:5       下载免费PDF全文
Delay consideration has been a major issue in design and test of high performance digital circuits.The assumption of input signal change occurring only when all internal nodes are stable restricts the increas of clock frequency.It is no longer true for wave pipelining circuits.However,previous logical delay models are based on the assumption.In addition,the stable time of a robust delay test generally depends on the longest sensitizable path delay.Thus,a new delay model is desirable.This paper explores th necessity first.Then,Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed.The concept of sensitization is redefined precisely in this paper.Based on the new concept of sensitization,an analytical delay model is introduced.As a result,many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points.The longest sensitizable path length is computed for circuit design and delay test.  相似文献
4.
面向对象程序设计语言的绑定时间分析技术   总被引:5,自引:0,他引:5       下载免费PDF全文
廖湖声  童兆丰  王众 《软件学报》2003,14(3):415-421
为了实现面向对象语言的部分求值,提出了一种绑定时间分析技术.该技术通过针对引用类型变量和指针变量的上下文敏感分析,能够比较精确地分析面向对象语言中诸如对象元素、数组元素等复杂数据结构元素的绑定时间,进而扩大了部分求值的作用范围.这种方法采用两层BTA环境来保存静态变量和局部变量的BTA状态,设置一种专用句柄来表示不同程序点创建的对象,进而采用这种句柄的集合表示引用类型变量的BTA状态.在为面向对象语言程序标注绑定时间信息的过程中,采用一个正向分析和一个反向分析过程,借助于BTA环境来跟踪和设定各种变量、对象和引用变量的绑定时间.该技术已经用于实现Java程序的绑定时间分析,能够有效地分析大多数单线程的Java程序,为实现高性能Java程序部分求值提供了必要的手段.  相似文献
5.
双阈值CMOS电路静态功耗优化   总被引:4,自引:0,他引:4  
集成电路设计进入深亚微米阶段后,静态功能不容忽视,提出一种基于双阈值电压的静态功耗优化算法,利用ISCAS85和ISCAS89电路集的实验结果表明,20%以上的静态功耗可以被消除(大规模电路在90%以上)。同时,文中算法也从很大程度上减小了电路的竞争冒险,提高了电路的性能。  相似文献
6.
Worst Case Execution Time Analysis for a Processor with Branch Prediction   总被引:4,自引:0,他引:4  
The fundamental requirement for hard real-time systems is that task deadlines be never missed. As a consequence, knowing tasks worst case execution times (WCET) is crucial for such systems. Taking into account modern architectural features makes it possible to determine tighter WCET bounds than with program analysis that ignores such features. While effects of caches and pipelines on WCET analysis have been extensively studied, to our knowledge the effect of the branch prediction on WCET evaluation has not been studied yet. This paper describes a method for statically bounding the number of timing penalties due to erroneous branch predictions. The proposed method is based on static program analysis and branch target buffer modelling. It consists in collecting information on branch target buffer evolution by considering all possible execution paths of a program. Collected information can then be used to classify control transfer instructions so that their worst case branching cost can be estimated and incorporated into the program WCET. A method is also given to tightly predict the WCET of loops whose number of iterations depend on counter variables of outer loops. Experimental results show that the timing penalty due to wrong branch predictions estimated by the proposed technique is close to the real one, which demonstrates the practical applicability of our method.  相似文献
7.
Automatic control applications are real-time systems which pose stringent requirements on precisely time-triggered synchronized actions and constant end-to-end delays in feedback loops which often constitute multi-rate systems. Motivated by the apparent gap between computer science and automatic control theory, a set of requirements for real-time implementation of control applications is given. A real-time behavioral model for control applications is then presented and exemplified. Important sources and characteristics of time-variations in distributed computer systems are investigated. This illuminates key execution strategies to ensure the required timing behavior. Implications on design and implementation and directions for further work are discussed.  相似文献
8.
FPGA最小延时工艺映射理论及算法   总被引:4,自引:0,他引:4       下载免费PDF全文
彭宇行  陈福接 《软件学报》1996,7(10):626-633
本文以动态规划和网络流理论为基础,提出一种新的求解基于LUT结构的FPGA工艺映射算法,并证明了它能获得最小延时目标电路,算法计算复杂度低.  相似文献
9.
Controller Area Network (CAN) is used extensively in automotive applications, with in excess of 400 million CAN enabled microcontrollers manufactured each year. In 1994 schedulability analysis was developed for CAN, showing how worst-case response times of CAN messages could be calculated and hence guarantees provided that message response times would not exceed their deadlines. This seminal research has been cited in over 200 subsequent papers and transferred to industry in the form of commercial CAN schedulability analysis tools. These tools have been used by a large number of major automotive manufacturers in the design of in-vehicle networks for a wide range of cars, millions of which have been manufactured during the last decade. This paper shows that the original schedulability analysis given for CAN messages is flawed. It may provide guarantees for messages that will in fact miss their deadlines in the worst-case. This paper provides revised analysis resolving the problems with the original approach. Further, it highlights that the priority assignment policy, previously claimed to be optimal for CAN, is not in fact optimal and cites a method of obtaining an optimal priority ordering that is applicable to CAN. The paper discusses the possible impact on commercial CAN systems designed and developed using flawed schedulability analysis and makes recommendations for the revision of CAN schedulability analysis tools. Robert I. Davis received a DPhil in Computer Science from the University of York in 1995. Since then he has founded three start-up companies, all of which have succeeded in transferring real-time systems research into commercial product. At Northern Real-Time Technologies Ltd. (1995–1997) he was responsible for development of the Volcano CAN software library. At LiveDevices Ltd. (1997–2001) he was responsible for development of the Real-Time Architect suite of products, including an OSEK RTOS and schedulability analysis tools. In 2002, Robert returned to the University of York, and in 2004 he was involved in setting up a spin out company, Rapita Systems Ltd., aimed at transferring worst-case execution time analysis technology into industry. Robert is a member of the Real-Time Systems Research Group at the University of York, and a director of Rapita Systems Ltd. His research interests include scheduling algorithms and schedulability analysis for real-time systems. Alan Burns is head of the Real-Time Systems Research Group at the University of York. His research interests cover a number of aspects of real-time systems including the assessment of languages for use in the real-time domain, distributed operating systems, the formal specification of scheduling algorithms and implementation strategies, and the design of dependable user interfaces to real-time applications. He has authored/co-authored over 370 papers and 10 books, with a large proportion of them concentrating on real-time systems and the Ada programming language. Professor Burns has been actively involved in the creation of the Ravenscar Profile, a subset of Ada”s tasking model, designed to enable the analysis of real-time programs and their timing properties. Reinder J. Bril received a B.Sc. and an M.Sc. (both with honours) from the University of Twente, and a Ph.D. from the Technische Universiteit Eindhoven, the Netherlands. He started his professional career in January 1984 at the Delft University of Technology. From May 1985 until August 2004, he was with Philips, and worked in both Philips Research as well as Philips’ Business Units. He worked on various topics, including fault tolerance, formal specifications, software architecture analysis, and dynamic resource management, and in different application domains, e.g. high-volume electronics consumer products and (low volume) professional systems. In September 2004, he made a transfer back to the academic world, to the System Architecture and Networking (SAN) group of the Mathematics and Computer Science department of the Technische Universiteit Eindhoven. His main research interests are currently in the area of reservation-based resource management for networked embedded systems with real-time constraints. Johan J. Lukkien has been head of the System Architecture and Networking Research group at Eindhoven University of Technology since 2002. He received an M.Sc. and a Ph.D. from Groningen University in the Netherlands. In 1991, he joined Eindhoven University, after two years leave at the California Institute of Technology. His research interests include the design and performance analysis of parallel and distributed systems. Until 2000 he was involved in large-scale simulations in physics and chemistry. Since 2000, his research focus has shifted to the application domain of networked resource-constrained embedded systems. Contributions of the SAN group are in the area of component-based middleware for resource-constrained devices, distributed co-ordination, Quality of Service in networked systems and schedulability analysis in real-time systems.  相似文献
10.
实时系统软件设计方法   总被引:3,自引:0,他引:3  
讨论了实时系统软件工程方法、软件实现、调度与执行时间分析、系统软件验证四个方面的问题 ,介绍了在实时系统研究领域的学者们所做的工作 ,该领域理论的发展以及有待解决的问题。  相似文献
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