数据中心计算环境应用承载能力评价

随着新型计算服务模式在数据中心的普及,针对如何有效评价其承载能力的问题,提出一种新的应用承载能力评价体系和评价模型,具体分析了网络、计算资源对服务环境的影响度,并给出了实例分析。实例分析结果表明,新的评价体系和评价模型可以有效评估计算服务模式对各类信息服务系统部署运行的应用承载能力,进而提升信息服务保障整体效益。     

Embedding a fault-free hamiltonian cycle in a class of faulty generalized honeycomb tori

Generalized honeycomb torus (GHT) is recognized as an attractive alternative to existing torus interconnection networks in parallel computing systems. Assume that m and d are integers with m ? 2 and d ? 8. This paper addresses the fault-tolerant hamiltonicity of GHT(m, 2d, d) with fault set F = {(w, y), (x, y)}, where w < x, w + y is even and x + y is odd. We show that such a faulty GHT is hamiltonian by presenting a systematic method for constructing a fault-free hamiltonian cycle. This result reveals another appealing feature of GHTs.     

A parallel preconditioned conjugate gradient solution method for finite element problems with coarse–fine mesh formulation

The object of this paper is a parallel preconditioned conjugate gradient iterative solver for finite element problems with coarse-mesh/fine-mesh formulation. An efficient preconditioner is easily derived from the multigrid stiffness matrix. The method has been implemented, for the sake of comparison, both on a IBM-RISC590 and on a Quadrics-QH1, a massive parallel SIMD machine with 128 processors. Examples of solutions of simple linear elastic problems on rectangular grids are presented and convergence and parallel performance are discussed.     

一种基于P系统的图像阈值分割方法

将P系统引入到图像阈值分割中,提出了一种基于P系统的图像阈值分割方法。采用一个两层膜的组织型P系统作为其计算框架,每个膜作为独立的并行计算单元,速度一位置模型作为进化规则,同时采用同向／反向转运规则交换和共享膜之间的对象。实验结果表明,这个基于P系统框架的阈值分割方法具有可用性和有效性,能为图像寻找最优的分割阈值。     

Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

The parallelism attained by the use of Field Programmable Gate Arrays (FPGAs) has shown remarkable potential for accelerating control systems applications. This comes at a time when well established methods based on inherited serial Central Processor Units (CPUs) cannot guarantee solutions for the increasing execution speed demands. However, the transition from serial to parallel architectures represents a tremendous challenge due to overwhelming numbers of unexplored options and conflicting factors. The work presented achieves a parallelisation characterisation for generic MIMO systems using stand-alone FPGA implementations. The main contribution is that a very fine subset of possible serial/parallel implementations is obtained. This is used to achieve a flexible trade-off between cost and performance. Automatic optimisation of latency, occupied FPGA area and execution speed is attained and justified in respect to most of the feasible scenarios.     

Context Switching in a Run-Time Reconfigurable System

A distinguishing feature of reconfigurable computing over rapid prototyping is its ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context-switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment.     

A Scalable Interconnection Network Architecture for Petaflops Computing

Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus (2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N ² nodes. Each node is connected to one horizontal and one vertical 1D SOME-Bus. Each of N nodes connected to one 1D SOME-Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME-Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME-Bus, the 1D SOME-Bus, the crossbar and the torus under the message-passing paradigm.     

普适计算中的上下文及纯方位定位模型

室内高精度定位问题是普适计算中位置感知研究的首要难题。介绍了普适计算中上下丈的概念,就上下文中的位置问题进行了探讨。通过分析目前室内定位中存在的问题,给出了一种利用红外无源定位技术定位的模型,通过测得的方位角计算出用户的位置。对该模型进行了证明,证明结果显示该模型可以定出目标的准确位置。     

移动数据库技术及其在军事领域的应用研究

首先介绍了移动数据库和移动计算的基本原理,接着讨论了该技术在军事领域应用时应解决的关键技术,给出了军事应用的硬件性能、信息实时性及数据安全性等技术要求,最后归纳了该技术在军事领域的典型应用,并指出了该领域的一些热点和难点问题。