Electrochemical intercalation into graphite seen as an electrocapillary process

The electrochemical intercalation of H₂SO₄ into graphite leads to the well known graphite salts C⁺_n HSO⁻₄. χH₂SO₄ (with n → 20), χ ≈ 2.5). The potential—charge relations observed during intercalation agree well with a model involving the extended graphene layer-intercalate interfacial capacitance. The components of this capacitance are studied, including the effect of Fermi level lowering. A computed electrocapillary curve is compared to the separation work of graphene layers.     

Integration of GPU Computing in a Software Radio Environment

This article studies the integration of Graphics Processing Units in a Software Defined Radio environment. Two main solutions are considered, based on two levels of granularity for the parallelization. First, a fine grain parallelism solution, which is an extension of the existing solutions but adapted to operations of large computational complexity, is proposed. Second, an original solution based on coarse grain approach allowing better usage of the computing resources and easier parallelism extraction is described. For both solutions, scheduling and communication design as well as implementation are given, along with integration in the environment. Both solutions have been implemented and compared on different operations types and on multi-operations sequences. It is clearly shown that using the second solution can provide performance improvement, while the first one is not adapted to SDR applications.     

Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.     

Hardware/software support for adaptive work-stealing in on-chip multiprocessor

During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue this computational and flexibility trend is the generalization of on-chip multiprocessor platforms (MPSoC). In that context, choosing a programming model and providing optimized hardware support to it on these platforms is a challenging task. To deal in a portable way with MPSoCs having a different number of processors running possibly at different frequencies, work-stealing (WS) based parallelization is a current research trend.The contribution of this paper is to evaluate the impact of some simple MPSoCs’ architecture characteristics on the performance of WS in the MPSoC context. The previous evaluations of WS, either theoretical or experimental, were done on fixed multicores architectures. This work extends these studies by exploring the use of WS for the codesign of embedded applications on MPSoC platforms with different hardware capabilities, thanks to cycle-accurate measures.We firstly study the architectural choices suited to WS algorithms and measure the benefit of these architectural modifications. To assert whether WS is suited to the MPSoC context, we experimentally measure its intrinsic implementation overhead on the most efficient architectural designs. Finally, we validate the performances of the approach on two real applications: a regular multimedia application (temporal noise reduction) and an irregular computation intensive application (frames of the Mandelbrot set).Our results show that enhancing MPSoC platforms having up to 16 processors with widespread hardware support mechanisms can lead to important performance improvements at acceptable hardware cost for the considered applications.     

Lightweight Transactional Memory systems for NoCs based architectures: Design,implementation and comparison of two policies

Hardware Transactional Memory (HTM) is an attractive design concept which simplifies parallel programming by shifting the problem of correct synchronization between threads to the underlying hardware memory system.     

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

This paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic.     

Deterministic reversible MPSoC debugger based on virtual platform execution traces

The increasing complexity of multiprocessor system on chip (MPSoC) makes the software developers life harder when chasing bugs. The debugging process is particularly tedious as it involves analyzing parallel execution flows. Executing a program many times is an integral part of the process in conventional debugging, but the non-determinism due to parallel execution often leads to different execution paths and different behaviors. In this paper, we propose an approach based on simulation, as it is nowadays an integral part of the MPSoC design flow, to ease pin-pointing bugs in a parallel execution. To that aim, we collect traces using a virtual platform, and when an execution fails, re-execute the traces, in either forward or reverse direction. We define a trace model suitable for this task, and detail a strategy for providing forward and reverse execution features to avoid long simulation times during a debug session. We demonstrate experimentally that re-execution is a deterministic process which, when debugging using the usual trial and error developer approach, is much faster than simulation.     

Multi-Material 3D Microprinting of Magnetically Deformable Biocompatible Structures

Two-photon polymerization (2PP) allows precise 3D printing at the micrometer scale, and by associating it with magnetic materials, the creation of remotely actuatable micro-structures. Such structures attract a growing interest for biomedical applications, thanks to their size and to the biocompatibility of some photoresist materials. Gelatin methacryloyl (Gel-MA) is one such material, and can be used to create physiological scaffolds for cell culture. Here, the physico-chemical properties of two resins are exploited, the first being a silica-based hybrid polymer, the OrmoComp, and the second a Gel-MA-based hydrogel. A 2PP manufacturing protocol is defined and designed to print both materials in succession as a single structure, which is then linked to a neodymium-iron-boron (NdFeB) magnetic bead for actuation. By this combination, a magnetically deformable 3D culture substrate is created to study cells in an environment that mimics soft, curved, and dynamic properties of tissues in vivo. The structure is actuated via an external magnetic field and bends back and forth along its longest axis. Lastly, preliminary cell culture trials are conducted showing the proliferation of cells on the structures.