Constrained model predictive control of proton exchange membrane fuel cell

A constrained model predictive control (MPC) is designed to regulate the air flow rate of proton exchange membrane fuel cell (PEMFC). Oxygen excess ratio, compressor flow rate and supply manifold pressure are constrained to avoid oxygen starvation, surge and choke phenomena. This is achieved by manipulating compressor voltage and stack current. The choice of the manipulated input to satisfy a constraint is investigated. Surge and choke avoidance is successful, when compressor voltage is manipulated. When stack current is utilized to satisfy surge and choke constraints, a large unrealistic current is needed. Oxygen starvation is successfully avoided utilizing stack current, while compressor voltage manipulation fails to prevent oxygen starvation. Thus, a current governor is implemented to handle oxygen starvation, while the compressor voltage is constrained to avoid surge and choke. Quadratic programming optimization, Laguerre and exponential weight function are employed to reduce the computational burden of the controller. The simulation results prove that the proposed controller managed to satisfy all constraints without any conflict.     

Deposition thickness based high-throughput nano-imprint template

International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60 nm [<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123-R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46-55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.     

Mobility improvement after HCl post-deposition cleaning of high-/spl kappa/ dielectric: a potential issue in wet etching of dual metal gate Process technology

The effect of deionized water and dilute hydrochloric acid, 500:1 (HCl) post-Hf-silicate deposition cleaning on the device characteristics of Hf-silicate MOSFETs have been investigated. The results suggest that a significant improvement in mobility and equivalent oxide thickness scaling can be obtained using HCl post-treatment in comparison to control and H/sub 2/O post-treated devices. The enhancement in bulk trapping immunity has been attributed to the reduced charge trapping in the bulk high-/spl kappa/ layers, whereas no apparent change in interface properties could be observed. The effect of the post-deposition cleaning might have important implications on the wet etching of gate metals in dual-metal-gate technology.     

Nonmetric calibration of camera lens distortion: differential methods and robust estimation.

This paper addresses the problem of calibrating camera lens distortion, which can be significant in medium to wide angle lenses. Our approach is based on the analysis of distorted images of straight lines. We derive new distortion measures that can be optimized using nonlinear search techniques to find the best distortion parameters that straighten these lines. Unlike the other existing approaches, we also provide fast, closed-form solutions to the distortion coefficients. We prove that including both the distortion center and the decentering coefficients in the nonlinear optimization step may lead to instability of the estimation algorithm. Our approach provides a way to get around this, and, at the same time, it reduces the search space of the calibration problem without sacrificing the accuracy and produces more stable and noise-robust results. In addition, while almost all existing nonmetric distortion calibration methods needs user involvement in one form or another, we present a robust approach to distortion calibration based on the least-median-of-squares estimator. Our approach is, thus, able to proceed in a fully automatic manner while being less sensitive to erroneous input data such as image curves that are mistakenly considered projections of three-dimensional linear segments. Experiments to evaluate the performance of this approach on synthetic and real data are reported.     

Ageing of SiC JFET transistors under repetitive current limitation conditions

In power applications using normally on transistors, short circuit or current limitation modes can be recurrent during operation, especially when powering converters. So, studying the robustness of these devices under such severe condition is an important issue. The paper presents ageing tests of normally on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit operations. Experimental tests are detailed and the evolution of electrical parameters during ageing is presented. Especially, the evolution during tests of ageing indicators like on-state resistance and saturation current is presented. Numerical investigations have been performed in order to estimate temperature during short circuit operation and to quantify the effect of the maximum temperature on the ageing process.     

Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.     

Particle adhesion and removal mechanisms in post-CMP cleaning processes

Chemical mechanical polishing (CMP) is considered as the paradigm shift that enabled optical photolithography to continue down to 0.12 /spl mu/m. Currently, the polishing physics is not well defined though it is known that the nature of the process makes particle removal after CMP difficult and necessary. It is important to understand the particle adhesion mechanisms resulting from the polishing process and the effect-of the adhering force on particle removal in post-CMP cleaning processes. In this paper, strong particle adhesion is shown to be caused by chemical reactions (after initial hydrogen bonding) that take place in the presence of moisture and long aging time. In particle removal using brush cleaning, contact between the particle and the brush is essential to the removal of submicron particles. In noncontact mode, 0.1-/spl mu/m particle can hardly be removed when the brush is more than 1 /spl mu/m away from the particle. While in full contact mode, removal is possible for a 0.1-/spl mu/m particle at the investigated brush rotational speeds. The experimental data shows that high removal efficiency (low number of defects) is possible with a high brush pressure and a short cleaning time.     

Plasma-Induced Damage in High-k/Metal Gate Stack Dry Etch

Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution