Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.     

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.     

Digital time‐modulation pixel memory circuit in LTPS technology

Abstract— A digital time‐modulation pixel memory circuit on glass substrate has been designed and verified for a 3‐μm low‐temperature polysilicon (LTPS) technology. From the experimental results, the proposed circuit can generate 4‐bit digital codes and the corresponding inversion data with a time‐modulation technique. While the liquid‐crystal‐display (LCD) panel operates in the still mode, which means the same image is displayed on the panel, a data driver for an LCD panel is not required to provide the image data of the frame by the proposed pixel memory circuit. This pixel memory circuit can store the frame data and generate its corresponding inversion data to refresh a static image without activating the data driver circuit. Therefore, the power consumption of a data driver can be reduced in the LCD panel.     

Dynamic modeling of a multiple hearth furnace for kaolin calcination

A dynamic model of a multiple hearth kaolin calciner has been developed and is presented in this article. This model describes the physical‐chemical phenomena taking place in the six furnace parts: the solid phase, gas phase, walls, cooling air, rabble arms, and the central shaft. The solid phase movement, in particular, is described by a novel mixing model. The mixing model divides the solid bed in a hearth into volumes and the distribution of their contents, after one full central shaft rotation, is identified by the pilot experiments. First, the model is validated by the industrial data, and then the dynamics of the multiple hearth furnace is studied by introducing step changes to the three manipulated variables: the feed rate, and the gas, and air flows supplied. The responses of the gas phase temperature and solid bed component profiles are analysed and the results are discussed. © 2015 American Institute of Chemical Engineers AIChE J, 61: 3683–3698, 2015     

Implementation of delta—sigma analog‐to‐digital converter in LTPS process

Abstract— An on‐panel delta—sigma analog‐to‐digital converter (ADC) has been implemented and verified for 3‐μm low‐temperature polysilicon (LTPS) technology with two basic blocks: a delta—sigma modulator and a decimation filter. From the experimental results, the digital output from the delta—sigma modulator is correctly matched with the analog input voltage ratio such that the digital output can be converted into 8‐bit digital code successfully under a supply voltage of 10 V from the decimation filter. The implemented on‐panel delta—sigma ADC can be used for the application of temperature‐to‐digital converter on glass substrate.     

LMI OPTIMIZATION APPROACH FOR DELAY‐DEPENDENT H∞ CONTROL OF TIME‐VARYING DELAY SYSTEMS

In this paper, the robust delay‐dependent H_∞ control for a class of uncertain systems with time‐varying delay is considered. An improved state feedback H_∞ control is proposed to minimize the H_∞‐norm bound via the LMI optimization approach. Based on the proposed result, delay‐dependent criteria are obtained without using the model transformation technique or bounded inequalities on cross product terms. The linear matrix inequality (LMI) optimization approach is used to design the robust H_∞ state feedback control. Some numerical examples are given to illustrate the effectiveness of the approach.     

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness

New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout.