A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.     

一种集成新型相位切换预分频器和高品质因素压控振荡器5 GHz CMOS频率综合器

本文实现了一种集成新型相位切换预分频器和高品质因素压控振荡器的锁相环频率综合器。该频率综合器在考虑噪声性能的基础上进行系统参数设计。预分频器采用了一种不易受工艺偏差影响的相位切换方式。对压控振荡器的电感开关电容和压控电容的品质因素进行了优化。与其他文献相比,该频率综合器使用相近的功耗取得更好的噪声性能。本文提出的频率综合器采用SMIC0.13微米工艺流片,芯片面积为11502500 μm²。当锁定在5 GHz时,其功耗在1.2V电源电压供电时为15mA。此时,1MHz频偏处相位噪声为-122.45dBc/Hz。     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

一种饱和功率为21dBm，峰值效率为35%的应用于900MHz RFID阅读器的CMOS线性功率放大器

本文在CMOS 0.18μm Mixed Signal工艺上实现了工作于900MHz的两级差分线性功率放大器,该功放工作于class AB状态。本文探讨了低压下输出匹配和谐波抑制网络,以提高功放的输出功率及效率,降低输出谐波。测试结果表明,在1.8V的电源电压下,功放在900MHz频率的输出饱和功率达到21.1dBm,输出1dB压缩点的功率为18.4dBm,峰值功率增加效率为35.4%,功率增益为23.3dB,各谐波分量也得到很好的控制。两级功放加上PAD的芯片总面积为1.2×0.55mm2。通过单芯片测试以及基于原型机的测试结果表明,该功放可以满足UHF RFID阅读器的应用。     

一种0.13微米CMOS工艺1.0V差分压控振荡器设计

本文实现了一种集成高品质因素片上电感的差分互补压控振荡器。该压控振荡器的谐振腔由片上电感和反型MOS电容并联组成。谐振腔的品质因素主要被片上电感性能所限制。通过优化设计以及采用单圈的拓扑结构,片上电感在6GHz仿真的品质因素可以达到35。本文提出的压控振荡器采用SMIC0.13微米工艺流片,芯片面积为1.0×0.8mm2。振荡器的频率范围为5.73GHz到6.35GHz。当振荡器中心频率为6.35GHz时,其功耗在1.0V电源电压时为2.55mA,1MHz频偏处相位噪声为-120.14dBc/Hz。该压控振荡器的FOM值达到-192.13dBc/Hz.