应用于软件无线电的四阶可重构模拟基带滤波器

本文提出了一个应用于软件无线电的四阶可重构模拟基带滤波器。该滤波器采用有数字辅助的有源RC低通结构,可以灵活地改变滤波器的特性,比如截止频率,选择性,类型,噪声,增益和功耗。为了同时达到优化噪声和调节功耗的目的,这里采用了一种新的可配置运放结构。该芯片采用SMIC 0.13μm CMOS工艺制作。主体滤波器和频率校准电路的面积分别为1.8 × 0.8 mm2和0.48 × 0.25 mm2。测试结果表明,该滤波器可以提供巴特沃斯和切比雪夫两种响应,而且截止频率可以覆盖从280kHz 到15MHz的宽带范围,同时可调增益范围为0dB到18dB。在1.2V的电源电压下获得29dBm的IIP3。根据给定的协议,输入参考噪声密度在41 nV/Hz½ 到133 nV/Hz½之间变化,低频带和高频带模式分别消耗了5.46mW和8.74mW的功耗。     

Analysis and design of a 1.8-2.7 GHz tunable 8-band TDD LTE receiver front-end

This paper describes the analysis and design of a 0.13μm CMOS tunable receiver front-end that supports 8 TDD LTE bands,covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes.The novel zero-IF receiver core consists of a tunable narrowband variable gain low-noise amplifier(LNA),a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier,an LO divider,a rough gain step variable gain pre-amplifier,a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier.The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band,eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes.The test chip is implemented in an SMIC 0.13μm 1P8M CMOS process.The full receiver achieves 4.6 dB NF,-14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.     

1.8～2.7GHz可调谐八波段时分LTE多模接收机前端的分析与设计

摘要：本文阐述了支持八波段可调谐时分LTE多模接收机前端的分析与设计,覆盖1.8～2.7GHz频率范围并支持5/10/15/20MHz三种带宽和QPSK/16QAM/64QAM 三种调制方式。零中频可调谐接收机前端的设计包括了可调谐窄带可变增益低噪声放大器,电流型下变频混频器和二阶低通输出跨阻放大器,可变增益预放大器,可调谐四阶切比雪夫低通信道选择滤波器和截止频率矫正电路,中频可变增益放大器。 窄带低噪声放大器可以在调谐范围内自由调节中心频率,从而替代了传统多模接收机中的低噪声放大器阵列,节省了芯片面积。模拟基带部分也可以通过数字接口调节增益和信道选择带宽。芯片在SMIC 0.13μm 1P8M CMOS上实现,测试结果显示双边带噪声系数达到4.6dB, 带外IIP3达到-14.5dBm,30～94dB增益范围。1.2V电源电压下芯片消耗功耗为54mA。     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.