Fully integrated blue/UV SOI CMOS photosensor for biomedical and environmental applications

In this paper, we present a microsystem for measuring optical power in blue/UV wavelengths (from λ = 200 nm to λ = 450 nm) which includes a photodiode and the analog processing circuit of the photodiode signal, fully integrated in 2 μm SOI CMOS technology. The photodiode has a maximum responsivity for λ = 400 nm. Th photosensor functions as a current to frequency converter. Measurements of the microsystem illuminated by blue and UV LEDs demonstrate the good linear behavior, sensitivity and efficiency of the system.     

Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.     

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si:H photodiode

In this paper we first present the integration of amorphous silicon photodiodes with a fully depleted silicon on isolator (FD SOI) MOSFET circuit. Taking the advantage of the better subthreshold characteristic of FD SOI MOSFETs with respect to bulk devices, a very simple SOI circuit integrated with the amorphous silicon photodiode is presented to significantly improve the ratio of the circuit output current when the diode is illuminated to when it is not. The use of one additional reference source voltage to adjust the operating point of the photodiode, allows to obtain a very significant increase in this current ratio, much higher than what can be obtained using a simple diode. Circuit solutions used to amplify the diode current under illumination are usually more complicated and involve a capacitor or more transistors than the circuit we present. All the other properties of the photodetector, as its spectral characteristic and linear dependence of detection with light intensity are maintained. The circuit can also be used in conjunction with other circuits for further amplification and/or processing.     

Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs

As MuGFETs are promising contenders for the end of the silicon Roadmap, their high-temperature behaviour needs to be addressed. In this work we investigate the variations of the subthreshold slope (SS) of double-gate devices and MuGFETs with intrinsic doping as a function of the temperature and fin width. Focus is placed on the superlinear behaviour of SS occurring above a certain temperature threshold. Numerical simulations are performed using Comsol Multiphysics^™ and a 1D analytical model is developed. The model, which includes the effect of film and gate oxide thickness, is shown to accurately fit the numerical data. A new definition for the subthreshold slope under high-temperature operation is proposed. The high-temperature subthreshold slope degradation is shown to increase with fin width.     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

A new F(ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs

In this paper, we present 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics^? software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). We then use this new algorithm to explore the effect of local constrictions on the performance of nanowire MultiGate Field-Effect Transistors (MuGFETs). We show that cross-section variations in a nanowire result in the formation of energy barriers that can be used to improve the on/off current ratio and switching characteristics of transistors: (1) A small constriction resulting in a barrier of the order of a 0.1 eV can be used as an effective means to improve the subthreshold slope and minimize the on/off current ratio degradation resulting from SD tunneling in ultra scaled transistor, and (2) We also report a new variable barrier transistor (VBT) device concept that is able to achieve sub-kT/q subthreshold slope without using impact ionization or band-to-band tunneling. Intra-band tunneling through constriction barriers is used instead. The device is, therefore, fully symmetrical and can operate at very low supply voltages. A subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the widest current range reported so far.     

Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

A new concept of nanoscale MOSFET, the Gate Modulated Resonant Tunneling Transistor (RT-FET), is presented and modeled using 3D Non-Equilibrium Green’s Function simulations enlightening the main physical mechanisms. Owing to the additional tunnel barriers and the related longitudinal confinement present in the device, the density of state is reduced in its off-state, while remaining comparable in its on-state, to that of a MOS transistor without barriers. The RT-FET thus features both a lower RT-limited off-current and a faster increase of the current with V_G, i.e. an improved slope characteristic, and hence an improved I_on/I_off ratio. Such improvement of the slope can happen in subthreshold regime, and therefore lead to subthreshold slope below the kT/q limit. In addition, faster increase of current and improved slope occur above threshold and lead to high thermionic on-current and significant I_on/I_off ratio improvement, even with threshold voltage below 0.2 V and supply voltage V_dd of a few hundreds of mV as critically needed for future technology nodes. Finally RT-FETs are intrinsically immune to source-drain tunneling and are therefore promising candidate for extending the roadmap below 10 nm.     

Active fault tolerant control for switched positive linear systems

The main aim of this paper is to design an active fault tolerant controller for switched positive linear systems. A theorem is proved for fault and state estimation of switched positive linear systems in terms of matrix inequality by considering average dwell‐time approach. By utilizing the theorem results, not only a fast and exact estimation of fault and state is obtained but also the positivity of state estimation is ensured. The feasibility problem is solved by formulating it into a special sequential optimization problem subject to LMI constraints. Based on the fault estimation information, an observer‐based fault tolerant control guaranties the stability and positivity of the closed‐loop system. Finally, a practical example including a data communication network is presented to illustrate the efficiency of the proposed method.     

Optimal non‐blocking decentralized supervisory control with unobservable controllable events

Paranormality is an observation property of a language, in which the occurrence of unobservable events never exits the closure of the language. In this paper, a synthesis method is proposed to construct a paranormal supervisor. We propose a method to construct a controllable language such that the occurrence of unobservable events does not exit the closure of the controllable language. Moreover, a new observation property, that is, Quasi Output Control Consistency (QOCC) is defined to construct the optimal (least restrictive) non‐blocking decentralized supervisory control in the presence of unobservable controllable events. Using QOCC and natural observer properties, we propose a method to construct a normal supervisor such that an arbitrary pair of lookalike strings are initiated and terminated with identical observable and uncontrollable events. It is assumed that one of these strings has unobservable controllable events. An OCC property is defined in the literature as a special case of QOCC property, where none of the lookalike strings has unobservable controllable events.     

NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs

Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40 nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V_GS = V_TH.