Fuzzy logic-based pre-classifier for tropical wood species recognition system

Classifying tropical wood species poses a considerable economic challenge and failure to classify the wood species accurately can have significant effects on timber industries. The problem of wood recognition is compounded with the nonlinearities of the features among the similar wood species. Besides that, large wood databases presented a problem of large processing time especially for online wood recognition system. In view of these problems, we propose the use of fuzzy logic-based pre-classifier as a means of treating uncertainty to improve the classification accuracy of tropical wood recognition system. The pre-classifier serve as a clustering mechanism for the large database simplifying the classification process making it more efficient. The use of the fuzzy logic-based pre-classifier has managed to increase the accuracy of the wood recognition system by 4 % and reduce the processing time for training and testing by more than 75 % and 26 % respectively.     

Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using numerical optimization based o exhaustive search over the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to Madishetty et al. (IEEE Trans Circuits Syst I (Accepted, In Press), 2012a), this architecture shows a reduction of \(10\cdot n-3\) adder circuits, where \(n\) is the number of wavelet decomposition levels. Standard \(512\times 512\) images Mandrill, Lena, and Cameraman were submitted to digital realizations of both proposed algebraic integer based as well as fixed-point schemes, leading to quantifiable comparisons. The design is physically implemented for a 4-level 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device operating at up to a maximum clock frequency of 263.15 MHz. The FPGA implementation is tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis shows improved clock frequency of better than 500 MHz for a supply voltage of 1.1 V.     

2D space–time wave-digital multi-fan filter banks for signals consisting of multiple plane waves

Two dimensional space–time fan filters may be used for the highly-selective enhancement of spatio-temporal plane-waves on the basis of their directions of arrival. Unlike uniform bandwidth beam filters, ideal fan filters transmit passband signals over a range of directions of arrival that is independent of their 1D temporal spectrum. In this work, closed-form 2D wave-digital filter design equations and corresponding hardware architectures are proposed for realizing M independent fan-shaped passbands having independently steerable directionality and selectivity. A design method based on LCR ladder networks is proposed and implemented using a 2D time-multiplexed raster-scanned architecture that is suitable for low frequency applications such as audio, multimedia, seismic and ultrasonic beamforming. The architectures are designed, simulated, physically realized and tested on FPGA-based prototypes. Examples of 2D IIR M-fan filterbanks with FPGA implementations, together with measured results from on-chip hardware verifications, show the successful design and hardware realization. The filterbanks and hardware architectures are shown to be suitable for real-time sensor-array beamforming applications using custom VLSI circuits.     

Influence of chromium and impurities on the grain- refining behavior of aluminum

The grain-refining behavior of high purity aluminum (HPA1) and commercial purity aluminum (CPA1) containing Fe and Si as impurities (<0.2 wt pct each) has been studied with and without the presence of Cr in small and large quantities (0.2 and 2 wt pct). The Al-5Ti-lB master alloy ingot (0.2 wt pct) was used as a grain refiner. The emphasis was on the influence of individual elements and their interactions with the other elements on the grain-refining behavior of Al. Good grain refinement with insignificant fading in CPA1 was observed in comparison to HPA1. Similar results were obtained with a small concentration of Cr in HPA1 in HPA1-0.2 wt pct Cr alloy. The CPA1 and HPA1-0.2 wt pct Cr alloy have given the best grain-refining results among all the cases studied. A combination of small quantities of Fe, Si, and Cr (CPA1-0.2 wt pct Cr) has shown early and significant fading. A large concentration of Cr (2 wt pct) has shown a poisoning effect irrespective of the presence or absence of impurities such as Fe and Si in Al. Thus, Cr was found to be beneficial for grain refinement at smaller concentrations in the absence of impurities. But at higher concentrations of Cr, it had an adverse effect,i.e., led to coarser grain sizes both in the presence and absence of impurities.     

Using Quick‐Start to enhance TCP‐friendly rate control performance in bidirectional satellite networks

In the not so distant future, we envisage an Internet where the biggest share of capacity is used by streaming applications. To avoid congestion collapse from unresponsive flows calls for a robust and ubiquitous end‐to‐end multimedia congestion control mechanism, such as TCP‐friendly rate control (TFRC), which provides fair sharing with the other Internet traffic. This paper therefore analyses the implications of using rate‐adaptive congestion control over satellite links that utilize demand allocation multiple access (DAMA) to maximize satellite transponder utilization. The interaction between TFRC and DAMA is explored using simulations supported by fluidic flow models. The analysis shows that DAMA reduces the start‐up phase of TFRC, causing non‐negligible delays. To mitigate this problem, we propose a new cross‐layer method based on the Quick‐Start mechanism. This can accelerate the start‐up of multimedia flows by a judicious allocation of additional capacity derived from cross‐layer signalling. Copyright © 2009 John Wiley & Sons, Ltd.     

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

A systolic architecture has recently been proposed for implementing two‐dimensional infinite impulse response (IIR) space–time beam plane‐wave filters at a throughput of one‐frame‐per‐clock–cycle for such applications as real‐time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M‐frames‐per‐clock‐cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look‐ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock‐cycle limit of the very large‐scale integration (VLSI) technology, thereby potentially allowing multi‐GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array‐based real‐time prototype is described, tested and verified for the two‐phase case (M = 2) at a technology‐limited clock frequency of 50 MHz which corresponds to a throughput of 100 million‐frames‐per‐clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.     

A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer function. The systolic array enables real-time implementation of 3-D IIR frequency-planar filters at radio-frequency (RF) frame-rates and is therefore a suitable building block for 3-D IIR digital filters having beam- and cone-shaped passbands as required for smart-antenna-array beam-forming applications involving the broadband spatio-temporal filtering of plane-waves. The fixed-point systolic-array implementation have a throughput of OFPCC and the tested real-time prototype achieves frame (clock) sample frequencies of up to 90 MHz using one Xilinx Virtex-4 sx35-10ff668 FPGA device.      

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

Analysis of personal computer ride through capability during voltage sags

Voltage sags have emerged as one of the most serious power quality problems, particularly for sensitive equipments such as personal computers (PCs). It is a complex electronic computing device designed to be powered by a switch mode power supply (SMPS). This paper presents an investigation of vulnerability of PCs to voltage sags and development of methods to enhance the voltage sag ride through capability of PCs. Based on recent testing standards, extensive tests were conducted for a wide range of PCs. For standard reboot/restart malfunction criterion, sag depth and duration were varied to construct individual voltage immunity curves for PCs. Based on the analysis, two methods were implemented to improve the voltage sag ride through capability of the PCs. These methods include the use of additional dc capacitors and alteration of the under voltage detection (UVD) signal in the housekeeping block of the SMPS. The experimental results on different PCs show that installation of additional capacitors can only expand PCs’ immunity duration to voltage sag while shift in the UVD signal helps to enhance the tolerance level in terms of sag magnitude. Finally, the advantages and disadvantages involved in the implemented methods to enhance voltage tolerance level of PCs are highlighted.