Transient behavior of subthreshold characteristics of fullydepleted SOI MOSFETs

It has been found that the subthreshold currents of fully depleted silicon-on-insulator (SOI) MOSFETs show a transient behavior under certain front-gate and back-gate voltage conditions. The cause of this anomaly is explained, and applications for the phenomenon are pointed out. Particularly, a simple way to measure the silicon film thickness is suggested     

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHzfT

We report room-temperature 0.07-μm CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V_dd=1.5 V and I_off ~2.5 nA/μm, minimum L_eff is about 0.085 μm for NFETs and 0.068 μm for PFETs. PFET I_on is 360 μA/μm, which is the highest value ever reported at comparable V_dd and I_off. The SOI MOSFET has about one order of magnitude higher I_off than a bulk MOSFET due to the floating-body effect. At around 0.07 μm L_eff, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications     

High-field transport of inversion-layer electrons and holesincluding velocity overshoot

In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Simulation of deep submicron SOI N-MOSFET considering the velocityovershoot effect

A set of numerical simulations were performed on 0.22 μm SOI MOSFET's with relatively uniform channel field and charge using the hydrodynamic model, the energy transport model, and the drift-diffusion model. The simulation results based on the advanced models (hydrodynamic and energy transport) show nearly identical results for the I-V characteristics and they agreed quite well with the experimental results, while the results from drift-diffusion model do not. Also the simulation results show that both the hydrodynamic and energy transport models handle the effect of velocity overshoot on the I-V characteristic of the 0.12 μm device well     

Recessed-channel structure for fabricating ultrathin SOI MOSFETwith low series resistance

A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFET's with low source/drain series resistance. Thin-film fully depleted SOI MOSFET's with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance     

PD/SOI SRAM performance in presence of gate-to-body tunneling current

This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.     

Transient pass-transistor leakage current in SOI MOSFET's

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Observation of velocity overshoot in silicon inversion layers

Employing a test structure, velocity overshoot in silicon inversion layers is observed at room temperature. For channel lengths longer than 0.3 μm, the velocity/field relation follows the well-known behavior with no channel length dependence. The first indication of velocity overshoot is seen at a channel length of 0.22 μm, while at L=0.12 μm, drift velocities up to 35% larger than the long-channel value are measured