An interpolating clock synthesizer

A digital alternative to analog phase-locked loop (PLL)-based clock generators for microprocessors, denoted an interpolating clock synthesizer (ICS), is described. Using ROM-based digital waveform synthesis, the ICS implements a wide range of frequency multiples having the form P/Q, where P and Q are integers. The ICS outputs two synthesized clocks, one for the I/O interface having a 1/1 frequency multiple and one for the core having one of eight dynamically-selectable frequency multiples (1/1, 3/2, 5/3, 2/1, 5/2, 3/1, 15/4, and 5/1). The ICS uses a synchronous delay line as a coarse (T_p/30) timing reference, while through digital delay interpolation it achieves a fine delay resolution of 0.04 ns. Using a completely digital precision phase detector, the ICS achieves a DC skew of ±0.05 ns     

Two novel fully complementary self-biased CMOS differentialamplifiers

Two CMOS differential amplifiers, one that is intended for applications in which the input common-mode range is relatively limited, the complementary self-biased differential amplifier (CSDA), and one that is intended for applications in which the input common-mode range is bounded only by the supply voltages, the very-wide-common-mode-range differential amplifier (VCDA), are discussed. Both differ from conventional CMOS differential amplifiers in having fully complementary configurations and in being self-biased through negative feedback. The amplifiers have been applied as precision high-speed comparators in commercial VLSI CMOS integrated circuits