Pixel design of pulsed CMOS image sensor for retinal prosthesis with digital photosensitivity control

A newly designed pulse frequency modulation photosensor for use in retinal prosthesis is proposed and demonstrated. The pixel converts the intensity of incident light into biphasic current pulses at frequencies suitable for the electrical stimulation of retinal neurons. Experimental results showed that the device was sensitive over a dynamic range of input light of about 120 dB, and that photosensitivity could be varied from 0 dB to around -40 dB.     

Dynamic range improvement by narrow-channel effect suppression andsmear reduction technologies in small pixel IT-CCD image sensors

Technologies for narrow-channel effect suppression in photodiodes (PDs) and vertical CCDs (V-CCDs) and for smear reduction in PDs have been developed in order to improve dynamic range in small pixel interline-transfer CCD (IT-CCD) image sensors. The new technologies have been applied to a progressive-scan IT-CCD image sensor with 5 μm square pixels and have (1) increased the charge handling capability of its V-CCDs to 4500 electrons/V; (2) improved its smear value to -95 dB; and (3) increased the saturation charge of its PDs to 2.3×10⁴ electrons     

Pulse frequency modulation based CMOS image sensor for subretinal stimulation

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16/spl times/16 pixels. Biphasic current stimulus pulses at above threshold levels of the human retina (500 /spl mu/A) at varying frame rates (4 Hz to 8 kHz) have been achieved. The implant chip was fabricated using standard CMOS technology.     

A 30 frames/s 2/3-in 1.3 M-pixel progressive scan IT-CCD imagesensor

A 30 frames/s 2/3-in 1.3 M-pixel progressive scan interline-transfer charge-coupled device (IT-CCD) image sensor has been developed for video and digital still-camera applications. To obtain high frame-rate images, a 49-MHz driving horizontal CCD (H-CCD) was developed. An 8-phase drive for vertical CCDs (V-CCDs) makes it possible to operate in a variety of modes, such as 1050 line progressive scan mode and 1049 line wide dynamic range interlaced scan mode. For digital still camera use, removing residual charges stored in the V-CCDs before exposure is essential, therefore new narrow-channel barrier over-flow drain (NCB-OFD) attached under the H-CCD was developed. The NCB-OFD automatically drains out extra charges and has the advantages of requiring neither an over-flow control gate nor any additional masks     

Optical limitations to cell size reduction in IT-CCD image sensors

We have determined the practical limits of cell size reduction in interline-transfer charge-coupled device (IT-CCD) image sensors, which result from diffraction occurring at the aperture above the photodiode. We have found that image cell size cannot be reduced to a level for which aperture width would fall below about 0.2 μm. We have also found, however that image cells with greater than 0.2 μm aperture size are sensitive over the entire wavelength range of visible light, and that sensitivity can be increased by thinning the photoshield film     

A 1/4-inch 380 k pixel IT-CCD image sensor employing gate-assisted punchthrough read-out mode

A newly developed 1/4-inch 380 k pixel IT-CCD image sensor features a novel cell structure in which signal charges are read out from a photodiode (PD) to a vertical-CCD (V-CCD) in a gate-assisted punchthrough mode. The cell structure, fabricated through the use of high energy ion implantation technology, enables both deep PD formation and transfer-gate (TG)/channel-stop (CS) length reduction. Deep PD formation helps increase sensitivity per PD unit area, and TG/CS length reduction widens both PD and V-CCD areas. Although the cell size is small (4.8 /spl mu/m (H)/spl times/5.6 /spl mu/m (V)), the sensor achieves both high sensitivity (35 mV/lx) and a high saturation signal (600 mV).<>     

High-sensitivity and no-crosstalk pixel technology for embeddedCMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si₃N₄ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light     

A signal-processing CMOS image sensor using a simple analog operation

We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) /spl times/384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3/spl times/9.3 /spl mu/m/sup 2/. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply.     

Pulse-domain digital image processing for vision chips employing low-voltage operation in deep-submicrometer technologies

A new architecture for pixel-level parallel image processing in the pulse domain for CMOS vision chips has been developed. Image processing such as edge enhancement, edge detection, and blurring are realized based on suppression and promotion of digital pulses; the pixel value is represented by the frequency of digital pulses by use of a pulse-frequency modulation (PFM) photosensor or that with an in-pixel 1-bit analog-to-digital converter. The proposed architecture is suitable for low-voltage operation in deep-submicrometer technologies because the image processing is implemented by 1-bit fully digital circuits with a small number of logic gates. The principles of the image processing are addressed. We have fabricated a 16 /spl times/ 16-pixel prototype vision chip. The relationship between illumination and the output pulse frequency is characterized. Step responses of the prototype vision chip for fundamental image processing operations show good agreement with those expected by correlation-based spatial filtering. A simple image binarization method specific to our architecture is also presented. The histograms of the intervals of the output pulses after image processing show multiple peaks, which indicates that averaging of the intervals is required for longer periods to achieve higher image-processing quality. To improve the linearity of pulse frequency dependence on illumination, usage of random clocks is discussed.