Low-power reduced transistor image sensor

An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s.     

Diagnostic value of ceruloplasmin, haptoglobin and sialic acid in chronic pyelonephritis

The widespread use of organophosphate pesticides creates the possibility of excessive exposure of migrant farm workers to these compounds. Blood cholinesterase determinations were used to compare the organophosphate pesticide exposure of 57 migrant farm workers with that of 35 controls. Frequently reported symptoms of the farm workers which might be related to pesticide exposure were also studied, including headaches, dizziness, loss of weight, nausea, and a general feeling of weakness or loss of energy. Significantly depressed cholinesterase activities were found in the farm workers, with 10.5% of the farm workers having values below the lower limit of normal. There was no significant relationship between frequently reported symptoms of the farm workers and depressed cholinesterase levels.     

Characterization of a visible spectrum division-of-focal-plane polarimeter

The development of high resolution division-of-focal-plane polarimeters in the visible spectrum allows real-time capture of two chief properties of interest, the degree of linear polarization and the angle of polarization. The accuracy of these two parameters can be influenced by a number of factors in the imaged scene, from the incident intensity and wavelength to the lens used for image capture. The alignment, transmission, and contrast ratios of the pixel matched filters also impact the measured parameters. A system of measurements is presented here that shows how these factors can determine the quality of a division-of-focal-plane polarimeter.     

Pipelined temporal difference imager

A 189×182 active pixel sensor for temporal difference computation is presented. The temporal difference imager, fabricated in an AM1 0.5 μm process, contains in-pixel storage elements for previous and current frames. A pipelined architecture for difference readout is implemented, allowing >200 fps, 42 dB signal-to-noise ratio images and 8-bit precision of the difference image. The chip consumes 30 mW at 50 fps from a 5 V power supply     

Programmable spatial processing imager chip

The authors present an architectural overview and results from an image processor chip for realising steerable spatial filtering at the focal plane. Convolutions of the image with multiple programmable kernels are realised with area-efficient, real-time circuits. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolutions are implemented with digitally programmable analogue processors. The chip performs 5.7 GOPS/mW while outputting four processed images in parallel     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

The anesthesiological risk and treatment characteristics of patients with ischemic heart disease prepared preoperatively with beta-receptor blockers, calcium antagonists and nitro preparations

The anesthesiologic risk in ischemic heart disease (IHD) patients undergoing noncardiac surgery is determined by the duration of myocardial infarction sustained in the past, and the degree (severity) of stenocardia manifestations. Such risk is estimated as minimal within six months after myocardial infarction in the presence of stenocardia stabilization. In this contingent of patients the anti-ischemic therapy is proceeded with in both pre- and postoperative period. The role of beta-adrenergic blocking agents (propranolol, acebutolol, esmolol, sotalol) and calcium antagonists (nifedipine, diltiazem) in the prophylaxis against intraoperative myocardial ischemia, rhythm disorders and pathologic arterial pressure rise is definitely proved.     

High Performance Biomorphic Image Processing Under Tight Space and Power Constraints

Image processing for space systems must be performed under tight space and power constraints while not compromising performance. Traditional computer vision approaches are not ideal because they are notoriously power hungry and physically large. We present two biologically inspired image processing systems that offer high performance on tight volume and power budgets. These systems follow a System-On-a-Chip (SOC) design methodology. They both exploit the promise of focal-plane computation offered by CMOS imaging technology.A general-purpose computational sensor has been fabricated in a standard 1.2 CMOS process, and its spatiotemporal filtering capabilities have been successfully tested. An array larger than 300 × 300 array will use only 0.5% of the chip area for the processing unit, while providing multiple spatiotemporally processed images in parallel. The 16 × 16 chip performs 1 GOPS/mW (5.5-bit scale-accumulate).An application specific sensor realizes a hybrid imaging system by combining a 120 × 36 low-noise active pixel sensor (APS) array with a 60 × 36 current mode motion detection and centroid localization array. The current mode array identifies pixels with time varying intensity. The centroid of all time varying pixels is computed. Clocked at greater than 60 fps, the chip consumes less than 2.5 mW.