A multilevel approach toward quadrupling the density of flashmemory

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake     

A novel Si/SiGe heterojunction pMOSFET with reduced short-channeleffects and enhanced drive current

A novel Si/SiGe bandgap engineered pMOSFET structure, called a high mobility heterojunction transistor (HMHJT), is proposed. Reduced short-channel effects and high drive current are predicted in this new device. Simulation results of devices with 100-nm physical gate lengths are presented. Physical effects are illustrated, and the performance is compared to the conventional Si devices. For low standby power or low leakage (high V_T) applications, the off-state leakage current due to drain induced barrier lowering (DIBL) or bulk punchthrough is substantially suppressed, and a very high I_on/I_off ratio of 6×10⁷ is obtained in a HMHJT without any anti-punchthrough implant. This ratio is a factor of 180 higher than that of a fabricated, conventional Si device with a similar threshold voltage found in the literature. On the other hand, for lower operating power (low V_T) applications, an HMHJT has a drive current 80% higher compared to an optimized Si device, while satisfying the same criteria for the off-state leakage current     

A convergence scheme for over-erased flash EEPROM's usingsubstrate-bias-enhanced hot electron injection

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved     

The Impact of Thermal Boundary Resistance in Phase-Change Memory Devices

Thermal conduction governs the writing time and energy of phase-change memory (PCM) devices. Recent measurements demonstrated large thermal resistances at the interfaces of phase-change materials with neighboring electrode and passivation materials. In this letter, electrothermal simulations quantify the impact of these resistances on the set to reset transition. The programming current decreases strongly with increasing boundary resistance due to increased lateral temperature uniformity, which cannot be captured using a reduced effective conductivity in the phase-change material. Reductions in programming current from 20% to 30% occur for an interface resistance of 50 m²middotK/GW. The precise spatial distribution of thermal properties is critical for the simulation of PCM devices.