Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs

A comparative investigation of high-energy neutrons effect on strained and non-strained devices with different geometries is presented. Both single-gate planar and multiple-gate (MuG) silicon-on-insulator (SOI) devices are considered. Device response to the neutron irradiation is assessed through the variations of threshold voltage and transconductance maximum. The difference between strained and non-strained device response to the high-energy neutrons exposure is clearly evidenced. The reasons for such a difference are discussed. Analysis of the experimental results allows for suggesting that strain relaxation is one of the probable causes.     

Study of the positive charge buildup into buried oxide of SIMOX SOI structure during bias–temperature stress

The buildup of fixed and mobile charge in the buried oxide (BOX) of silicon implanted by oxygen (SIMOX) silicon-on-insulator (SOI) structures during bias–temperature (BT) cycling has been studied by the thermally stimulated polarization (TSP) current technique and C–V measurements. Two polarization processes have been observed: the first process with activation energy of 0.3 eV is likely related to the positively charged ion transport across the BOX, the second process with activation energy about 1.2 eV is associated with space charge polarization. It was found that the ion transport is created simultaneously with the process of lateral positive charge buildup near the BOX/substrate interface when the bias is applied to the structure at temperatures above 280°C.     

Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects

In this letter, we modify the split capacitance-voltage technique to exclude the influence of floating-body effects on the extracted mobility values and extend its applicability by using the integral of transconductance measured at high frequencies instead of dc drain current values. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating-body effect, which is an inevitable feature of advanced silicon-on-insulator MOSFETs, but also to improve the general accuracy of mobility extraction in moderate-to-strong inversion regime. We demonstrate the advantages of our modified technique over the conventional one by applying it to partially depleted silicon-on-insulator devices from a FinFET process.     

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V/sub th/ deep-submicrometer 0.12-/spl mu/m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25/spl deg/C-220/spl deg/C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.     

Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs

It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.     

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity silicon substrates (HR-Si). Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps added to the mobility and carrier lifetime degradation, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation-induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide (t_ox = 50 nm), while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.