A recursive design methodology for VLSI: Theory and example

A novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT²) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance.     

Measuring Deep Metastability and Its Effect on Synchronizer Performance

Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude and events with long metastable times are selected from the large number of more normal events. The relationship found between input times and the resulting output times is dependent on accurate measurement of input time distributions with deviations of less than 10 ps. We show how the distribution of to clock times at the input can be characterized in the presence of noise and how predictions of failure rates for long synchronizer times can be made. Anomalies such as the increased failure rates in a master-slave synchronizer produced by the back edge of the clock are explained and demonstrated.     

Synchronous and asynchronous A-D conversion

Analog-digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. It is shown that an asynchronous converter in which the conversion time is not bounded is faster, on average, than the synchronous design. Real-time applications require the data to be produced within a fixed time, and failures may occur with the long conversion times that can arise with fully asynchronous converters. For these applications, we show that an internally asynchronous bounded time converter is both faster and more reliable than a synchronous converter     

Synchronization circuit performance

Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures (MTBF) is given. These effects can be explained by extending the existing theory to take account of initial offsets, and we propose a new, more accurate, formula. Synchronizer performance depends on achieving a high reliability of synchronization together with a short time. We show that commonly used circuits, such as the jamb latch, do not produce the best compromise for very high reliability applications, and that a better circuit can be designed. In order to confirm that thermal noise does not influence the MTBF against synchronization-time relationship, we have devised an experiment to measure noise in an integrated CMOS bistable circuit. We show that the noise exhibits a Gaussian distribution, and is close to the value expected from thermal agitation     

Time difference amplifier

Accurate measurement of edge time differences down to 10 ps or less is required for tests of timing in digital systems. A circuit is described that is aimed at reliably amplifying these time differences by a factor between 3 and 10 before measurement to enable greater accuracy.     

Effectiveness of computer-aided learning as a direct replacementfor lecturing in degree-level electronics

The application of computer-aided learning as a direct replacement for, as opposed to an adjunct to, lecturing is still in its infancy in higher education. This paper examines some of the reasons for its slow uptake and then describes a project to develop courseware for a large proportion of the electronic engineering syllabus within several UK higher education institutions. The first modules to be completed cover the area of computer engineering. The authors describe the philosophy and design of this courseware, and then report a series of tests in which the examination performance of students using it was compared with that of control groups taught in traditional lectures. The results clearly suggest that carefully designed courseware can lead to a large reduction in teaching time, with no significant difference in learning. They then describe the development of this courseware into what is believed to be the first degree-level electrical engineering course module to be replaced in its entirety by computer-based self-teaching. They discuss the impact of this development on the course structure, and show how the time gained has been used for additional practical work and tutorial support. Animated excerpts from this material are available by anonymous FTP     

An evaluation of asynchronous addition

There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low power, and device speed independence. An often quoted example of the speed improvement possible from self-timed hardware is parallel binary addition, where the carry signals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper shows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium