Smart sensor interface with A/D conversion and programmablecalibration

In this paper we present a new architecture for a smart sensor interface. It is based on an oversampled A/D converter associated with a small ROM containing calibration coefficients. The nonlinear function desired is obtained by piecewise linear interpolation between the values stored in the ROM, without any additional circuits. This solution has the advantage of high programming flexibility, long-term stability, and low area consumption. Moreover, it is suitable for co-integration with sensors because of its minimum analog content. A prototype was integrated in a CMOS 1.2-μm technology. Simulation and experimental results are reported together with a detailed theoretical analysis and some design guidelines     

A fourth-order single-bit switched-capacitor /spl Sigma/-/spl Delta/ modulator for distributed sensor applications

In this paper, we present a switched-capacitor sigma-delta (/spl Sigma/-/spl Delta/) modulator for high resolution applications. In particular, this /spl Sigma/-/spl Delta/ modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 /spl mu/m CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.     

A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm².     

Validation of data converter specifications with behavioral modeling simulations

The increasing complexity of data converter architectures makes it necessary to use behavioral models to simulate electrical performances and to determine the relevant data converter features. For this purpose, special input stimuli and specific output data processing are required. In view of that, it is necessary to offer a specific data-converter simulation environment that permit the designer to validate the data converter specification and to extract the basic blocks key features before starting the transistor level design. Pointed toward this objective, this paper analyses the most utilized architectures and identifies the basic (active and passive) building blocks used. Behavioral models of such basic blocks are discussed. The proposed behavioral models are then used in a pipeline and a Σ–Δ converter. Specific routines for the determination of data converter parameters are presented. Simulations show how specific features of basic blocks affect the overall performances. Thus, guidelines on how to design the circuit in order to meet specifications are given.     

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

A 2D micro-fluxgate earth magnetic field measurement systems with fully automated acquisition setup

In this paper we present an Earth magnetic field measurement system and an automated acquisition setup to characterize it. The measurement system consists of a fluxgate sensor and an integrated front-end circuit, both realized in CMOS technology. The couple of orthogonal axes of the sensor makes the system suitable for realizing an electronic compass device. Indeed, we can measure not only the amplitude of the Earth magnetic field (whose full-scale value is of the order of 60 μT), but also its direction. The complete measurement system achieves a maximum angular error of 1.5° in the measurement of the Earth magnetic field direction. Furthermore, an acquisition setup was developed to evaluate the measurement system performance. It consists of a precision mechanical plastic structure, in tower form, a microcontroller-based interface circuit, that provides a digital output through an RS232 serial interface, a PC software suitably developed to post-process the data from the acquisition system and a couple of Helmholtz coils to evaluate the linearity of the system. This setup allows us to perform a completely automated and numerically controlled characterization of the measurement system.     

A 1.0-mW, 71-dB SNDR,fourth-order ΣΔ interface circuit for MEMS microphones

In this paper an integrated interface circuit for condenser MEMS microphones is presented. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order ΣΔ modulator and a fully-digital, single-bit, fourth-order ΣΔ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3 V, exhibits a current consumption of 215 μA for the analog part and 95 μA for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog ΣΔ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-μm CMOS process, occupies an area of 3 mm², including pads.     

A 90 μW continuous-time front-end with 10b SAR-ADC for capacitive MEMS accelerometers

This paper presents a low power read-out front-end for 3-axis MEMS capacitive accelerometer. The front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation 10b A/D Converter, for digitalization and off-chip digital-signal-processing. Power minimization is achieved by using a continuous-time sensing preamplifier (i.e. constant-charge capacitance-to-voltage conversion) and SAR-ADC with bridge capacitive reduction. Preamplifier programmable in-band gain allows to accommodate different MEMS sensitivities. A very high-impedance MOS transistor is used for MEMS biasing, thus providing very low frequency (<1 Hz) AC coupling. In a 0.13 μm CMOS technology, the full channel consumes 90 μW from a single 1.2 V supply voltage, and achieves an equivalent 67.9 dB_Full-Scale@SNR in [1 Hz–4 kHz] bandwidth by exploiting oversampling ratio.